I was going through a document from Microsemi website (Actel HDL Code) and I found a few implementations of flip-flop (Synchronous, Asynchronous etc.).In all the cases the author has modelled the flip-flops with blocking statements.
I want to know are these implementations correct, because I have always used non blocking to model sequential logic? Am I missing something or is it just a way to model only flip flop and not a sequential circuit in general?
// Rising Edge Flip-Flop with Asynchronous Reset
module dff_async_rst (data, clk, reset, q);
input data, clk, reset;
output q;
reg q;
always #(posedge clk or negedge reset)
if (~reset)
q = 1'b0;
else
q = data;
endmodule
//Rising Edge Flip-Flop with Synchronous Reset
module dff_sync_rst (data, clk, reset, q);
input data, clk, reset;
output q;
reg q;
always # (posedge clk)
if (~reset)
q = 1'b0;
else
q = data;
endmodule
NOTE : Blocking assignments used in always block to get a sequential logic
Flip-flops should be modelled with non-blocking (<=) as you previously thought.
If your using any version of verilog after 1995 then your port declarations can be tidied up a little. NB I add begin ends for clarity and _n to designate active low signals.
Rising Edge Flip-Flop with Asynchronous Reset
module dff_async_rst (
input data,
input clk,
input reset_n,
output reg q //SystemVerilog logic is preferred over reg
);
always #(posedge clk or negedge reset_n) begin
if (~reset_n) begin
q <= 1'b0;
end
else begin
q <= data;
end
end
endmodule
Rising Edge Flip-Flop with Synchronous Reset
module dff_sync_rst(
input data,
input clk,
input reset_n,
output reg q //SystemVerilog logic is preferred over reg
);
always #(posedge clk) begin
if (~reset_n) begin
q <= 1'b0;
end
else begin
q <= data;
end
end
endmodule
Related
I've been designing a one-shot as part of my EE senior project and am unable to get the 'Reset' to toggle the output to 0.
I used the RTL_viewer in Quartus and the design does match my code: The DFF output (Q) is fed into 2 inverters then into the DFF Reset.
My understanding is that the two inverters should act as buffers. The DFF output should be 0 until the next clock edge is reached. I'm not sure if something is wrong with my design or if this is a timing error. I tried playing around with the clock speed and the buffer delay, but neither produced the correct results.
module oneShot(Clk, Q, Q_bar);
input Clk;
output Q, Q_bar;
logic X, Reset /* synthesis keep */;
logic D = 1'b1;
parameter propogation_delay = 30ns;
not #(propogation_delay) (X, Q);
not #(propogation_delay) (Reset, X);
//instantiation of flip flop
//DFF (Clk, Reset, D, Q);
DFF1 unit0 (Clk, Reset, D, Q);
assign Q_bar = ~ Q;
endmodule
module DFF1 (Clk, Reset, D, Q);
input Clk, Reset, D;
output logic Q;
always_ff #(posedge Clk)
begin
if(Reset == 1'b1)
Q <= 0;
else
Q <= D;
end
endmodule
module oneShot_tb;
logic Clk, Q, Q_bar, Reset;
oneShot DUT (Clk, Q, Q_bar);
always begin
Clk = 0;
#10;
Clk = 1'b1;
#10;
end
initial begin
#300;
$stop;
end
I write a D flip-flop module as below:
module mod1(
input clk,
input d,
output reg q
);
always #(posedge clk)begin
q <= d;
end
endmodule
These are the two code snippets I used to test my module mod1
// code 1
module mod1_tb;
reg clk;
reg d;
wire q;
mod1 dut(
.clk(clk),
.d(d),
.q(q)
);
always #10 clk = ~clk;
initial begin
clk = 0;
#(posedge clk)
d <= 0;
#(posedge clk)
d <= 1;
#(posedge clk)
d <= 0;
#(posedge clk)
d <= 1;
end
endmodule
The waveform can be seen like this:
// code 2
module mod1_tb;
reg clk;
reg d;
wire q;
mod1 dut(
.clk(clk),
.d(d),
.q(q)
);
always #10 clk = ~clk;
initial begin
clk = 0;
#(posedge clk);
d = 0;
#(posedge clk);
d = 1;
#(posedge clk);
d = 0;
#(posedge clk);
d = 1;
end
endmodule
The waveform can be seen like this:
In my view, all of them should work well, but the result shows that only the first way works.
I am a little confused about why the second one does not work.
The assumption is that your input signal (d) is synchronous to the clock. You should drive that signal in your testbench similarly to how it is driven in the design. Use #(posedge clk), as you are already doing, and use nonblocking assignments (<=) instead of blocking (=).
Your code 1 properly uses nonblocking in the testbench, which is why it simulates as you expect.
Your code 2 uses blocking in the testbench, which is why it does not simulate as expected.
The nonblocking assignment guarantees that the simulator will sample the synchronous input at the time you expect it to.
The recommended good coding practice is to use nonblocking for sequential logic, such as flip-flops.
There is plenty of literature out there which discusses the details of Verilog event scheduling. Here is one paper.
module rff_try_1(q,inp,clk);
input clk,inp;
output q;
reg q;
DFF dff0(q,inp,clk);
endmodule
module DFF(q,inp,clk);
input inp,clk;
output q;
reg q;
always # (posedge clk)begin
if(clk)begin
q=inp;
end
end
endmodule
here I'm using two modules but output is not coming
I'm trying to make two bit right shift register but 1st i have to make one single bit register but even this is not working
There are several mistakes in the code.
1) The line if(clk)begin and relevant end should be removed, posedge clk already describes trigger condition of the flip-flop.
2) A non-blocking assignment (<=) is required for the sequential logic.
The always block should be as follows:
always # (posedge clk) begin
q <= inp;
end
3) Some simulators don't complain, but signal q should be wire in module rff_try_1.
wire q;
Simulation
I simulated the code (after the modifications) on EDA Playground with the testbench below. Used Icarus Verilog 0.9.7 as simulator.
module tb();
reg clk = 1;
always clk = #5 ~clk;
reg inp;
wire q;
rff_try_1 dut(q, inp, clk);
initial begin
inp = 0;
#12;
inp = 1;
#27;
inp = 0;
#24;
inp = 1;
end
initial begin
$dumpfile("dump.vcd"); $dumpvars;
#200;
$finish;
end
endmodule
The signal q is as expected as seen on the waveform.
Hey guys so I written two Verilog modules, one is a state machine and the other is a counter that generates a pulse every half second for the machine to count.I tried to make a a top level design that would instantiate both modules, however when running a test bench, my state outputs would always equal to 'xx'. Any advice or help please?
COUNTER/PULSE:
module pulseit(clk, reset, pulse);
input clk, reset;
output pulse;
reg [25:0] count;
wire pulse;
always # (posedge clk, posedge reset)
if (reset) count <= 26'b0; else
if (pulse) count <= 26'b0; else
count <= count + 26'b1;
endmodule
STATE MACHINE:
module sm(clk, reset, in, state, pulse);
input clk, reset, in, pulse;
output [1:0] state;
reg [1:0] state, nstate;
always # (posedge clk, posedge reset)
if (reset) state <= 2'b0;
else state <= nstate;
always # (*)
begin
nstate = state;
if (pulse)
begin
case(state)
2'b00: nstate = (in)? 2'b01:2'b11;
2'b01: nstate = (in)? 2'b10:2'b00;
2'b10: nstate = (in)? 2'b11:2'b01;
2'b11: nstate = (in)? 2'b00:2'b10;
endcase
end
end
endmodule
TOPLEVEL:
module topLevel(clk, rst, in, state);
input clk, rst, in;
output [1:0] state;
reg [1:0] state;
wire y;
pulseit pull (.clk(clk), .reset(rst), .pulse(y));
sm machine (.clk(clk), .reset(rst), .in(in), .state(state), .pulse(y));
endmodule
While writing a module, it is a good practice for designer to ensure that all the ports must be driven from module. There may be intentional some left-outs of connection, but the major ports must be connected.
Here wire y is connected as an output pulse of pulseit module. But the output pulse is never driven. The pulseit module just increments count and that too it is dependent on pulse signal. Also the FSM module entirely depends on the pulse signal it gets as an input.
pulse needs to be driven by some logic inside pulseit module. I modified the pulseit module as follows and it works fine now:
module pulseit(clk, reset, pulse);
input clk, reset;
output pulse;
reg [25:0] count;
wire pulse;
always # (posedge clk, posedge reset)
if (reset) count <= 26'b0; else
if (pulse) count <= 26'b0; else
count <= count + 26'b1;
// Let's say pulse goes HIGH when 26th bit of count goes HIGH.
assign pulse = count[25]; // NEED TO DRIVE PULSE
endmodule
I have created a testbench for the above design at EDAPlayground for your reference. Some basic info about Verilog/SV modules can be found at this link and this link.
Note : When assigning, Array index must be in range of index to not overflow.
I was wondering if there is an easy way to define the active edge of a module, e.g. a register, in Verilog, so I can define if is positive/negative triggered when is instantiated. For example:
Register #(.width(8), .active_edge(`POS_EDGE)) DUT ();
This is my attempt, although, I don't know if it is even legal to use a logical operator in the posedge variable:
module Register #(
parameter width=8,
parameter active_edge=1'b1) (
input [width-1:0] D,
input clk, rst, we,
output reg [width-1:0] Q);
always #(posedge active_edge^~clk, posedge rst) begin
if (rst)
Q <= 'b0;
else
if (we) Q <= D;
end
endmodule
What you wrote is legal Verilog, but some synthesis tools might not accept a complex expression for the clock. You can write an intermediate expression and it will get optimized away.
module Register #(
parameter width=8,
parameter active_edge=1'b1) (
input [width-1:0] D,
input clk, rst, we,
output reg [width-1:0] Q);
wire local_clk = active_edge ? !clk : clk;
always #(posedge local_clock, posedge rst) begin
if (rst)
Q <= 'b0;
else
if (we) Q <= D;
end
endmodule