Verilog If else "Signal not a constant" error - verilog

Question

I am trying to instantiate modules inside various if else statements but i am getting the error with the first argument in the if parenthesis "signal is not a constant".All my arguments in the parenthesis of my if and if else statements are input wires,and i can't figure whats wrong
Thanks
I've tried passing the signals from a matrix to a single input for each position of the matrix but that didn't work either
Heres my some of my code below
The error is as follows:[Synth 8-35] 'neuron_valid11' is not a constant
`include "include.v"
module FeedForward(
//Input
input wire[`dataWidth-1:0] sensor1,
input wire[`dataWidth-1:0] sensor2,
input wire[`dataWidth-1:0] sensor3,
input wire[`dataWidth-1:0] sensor4,
input wire[`dataWidth-1:0] sensor5,
input wire[`dataWidth-1:0] sensor6,
input wire neuron_valid11,
input wire neuron_valid12,
input wire neuron_valid13,
input wire neuron_valid14,
input wire neuron_valid15,
input wire neuron_valid16,
input wire neuron_valid17,
input wire neuron_valid18,
input wire neuron_valid21,
input wire neuron_valid22,
input wire neuron_valid23,
input wire neuron_valid24,
input wire neuron_valid25,
input wire neuron_valid26,
input wire neuron_valid27,
input wire neuron_valid28,
input wire[(`dataWidth/2)-1:0] targetVals
);
wire [7:0] weightValue;
wire [7:0] biasValue;
wire [7:0] out;
integer Loop;
wire ActiveN1;
wire ActiveN2;
wire ActiveN3;
wire ActiveN4;
wire ActiveN5;
wire ActiveN6;
wire ActiveN7;
wire ActiveN8;
wire reset;
localparam IDLE = 'd0,
SEND = 'd1;
wire [`numNeuronLayer1-1:0] o1_valid;
wire [`numNeuronLayer1*`dataWidth-1:0] x1_out;
reg [`numNeuronLayer1*`dataWidth-1:0] holdData_1;
reg [`dataWidth-1:0] out_data_1;
reg data_out_valid_1;
if(neuron_valid11==1&&neuron_valid12==1&&neuron_valid13==1&&neuron_valid14==0&&neuron_valid15==1&&neuron_valid16==0&&neuron_valid17==0&&neuron_valid18==0)begin
Layer_1 #(.NN(`numNeuronLayer1),.numWeight(`numWeightLayer1),.dataWidth(`dataWidth),.layerNum(1),.sigmoidSize(`sigmoidSize),.weightIntWidth(`weightIntWidth),.actType(`Layer1ActType)) l1(
.ActiveN1(1),
.ActiveN2(1),
.ActiveN3(1),
.ActiveN4(0),
.ActiveN5(1),
.ActiveN6(0),
.ActiveN7(0),
.ActiveN8(0),
.clk(s_axi_aclk),
.rst(reset),
.weightValue(weightValue),
.biasValue(biasValue),
.sensor1(sensor1),
.sensor2(sensor2),
.sensor3(sensor3),
.sensor4(sensor4),
.sensor5(sensor5),
.sensor6(sensor6),
.o_valid(o1_valid),
.x_out(x1_out)
);
end

Answer 1

What you have written is
// If a wire equals 1
if(neuron_valid11==1...)begin
// Declare a module instance
Layer_1 #(..)(...);
end
You can't say 'while the design is running, if this wire has a certain value==1 then these modules exist in my design' - doesn't make sense. The module is a physical thing, fixed there or not, not popping in and out of existence.
You can at compile time do 'if MY_PARAM=SOMETHING begin, then instantiate your module' as long as the value is constant (as your error says). See https://www.chipverify.com/verilog/verilog-generate-block.
Or perhaps you want to select/mux signals into your module (maybe you want it disconnected/disabled sometimes and not others based on some condition). You would do that inside a always block, ex. checking if(neuron_valid11==1 and driving signals that connect to your (always-existing) module instance. https://www.chipverify.com/verilog/verilog-4to1-mux