I'm running into the following errors when trying to synthesize my code to run on my Anvyl board:
ERROR:HDLCompiler:329 - "C:/Users/Chase/Desktop/Code
Templates/final_bcd_counter.v" Line 25: Target <digit_1> of concurrent assignment or output port connection should be a net type.
ERROR:HDLCompiler:329 - "C:/Users/Chase/Desktop/Code
Templates/final_bcd_counter.v" Line 26: Target <digit_2> of concurrent assignment or output port connection should be a net type.
I was provided with a Lab_board.v file to drive the board which is as follows:
`timescale 1ns / 1ps
module lab_board(LED, SW, CLK);
output [7:0] LED;
input [7:0] SW;
input CLK;
bcd_count_7 counter(
.max_count(SW[6:0]),
.CLK(CLK),
.run(SW[7]),
.digit_l(LED[3:0]),
.digit_2(LED[7:4])
);
endmodule
The code that the errors are throw in is my final_bcd_counter.v file which is the main driver of the program that passes all the needed values to the board. It is as follows:
// This is the top module for the programmable BCD counter.
// It implements a programmable 7-bit counter and a binary-
// to-bcd converter that can output two digits.
module bcd_count_7(max_count, CLK, run, digit_1, digit_2);
input [6:0] max_count;
input CLK, run;
output reg [3:0] digit_1;
output reg [3:0] digit_2;
//Wires and registers for interconnect if needed
wire [6:0] countin_out;
// Programmable 7-bit counter module
prog_count_7 counter(.max_count(max_count),
.run(run),
.CLK(CLK),
.count_out(countin_out));
// Binary-to-BCD Converter for converting count_out to BCD
binary_bcd_2 bcd_converter(.bin_in(countin_out),
.digit_1(digit_1),
.digit_2(digit_2));
endmodule
I've tried changing the type of digit_1 and digit_2 with no avail. Could the solution be creating wires that connect to the lab board instead of passing output registers, if so, what would that look like?
Any help is appreciated. I can provide the code of the other modules in the program if needed.
Thanks!
You've declared digit_1/2 as a variable and it needs to be a net in Verilog I'm assuming those are output ports from your binary_bcd_2 module. SystemVerilog does not have this restriction.
Simply remove the reg keyword from the port declaration. I've added wire for clarity, but that is what is implicit
module bcd_count_7(
input wire [6:0] max_count,
input wire CLK, run,
output wire [3:0] digit_1,
output wire [3:0] digit_2
);
Related
I am trying to instantiate modules inside various if else statements but i am getting the error with the first argument in the if parenthesis "signal is not a constant".All my arguments in the parenthesis of my if and if else statements are input wires,and i can't figure whats wrong
Thanks
I've tried passing the signals from a matrix to a single input for each position of the matrix but that didn't work either
Heres my some of my code below
The error is as follows:[Synth 8-35] 'neuron_valid11' is not a constant
`include "include.v"
module FeedForward(
//Input
input wire[`dataWidth-1:0] sensor1,
input wire[`dataWidth-1:0] sensor2,
input wire[`dataWidth-1:0] sensor3,
input wire[`dataWidth-1:0] sensor4,
input wire[`dataWidth-1:0] sensor5,
input wire[`dataWidth-1:0] sensor6,
input wire neuron_valid11,
input wire neuron_valid12,
input wire neuron_valid13,
input wire neuron_valid14,
input wire neuron_valid15,
input wire neuron_valid16,
input wire neuron_valid17,
input wire neuron_valid18,
input wire neuron_valid21,
input wire neuron_valid22,
input wire neuron_valid23,
input wire neuron_valid24,
input wire neuron_valid25,
input wire neuron_valid26,
input wire neuron_valid27,
input wire neuron_valid28,
input wire[(`dataWidth/2)-1:0] targetVals
);
wire [7:0] weightValue;
wire [7:0] biasValue;
wire [7:0] out;
integer Loop;
wire ActiveN1;
wire ActiveN2;
wire ActiveN3;
wire ActiveN4;
wire ActiveN5;
wire ActiveN6;
wire ActiveN7;
wire ActiveN8;
wire reset;
localparam IDLE = 'd0,
SEND = 'd1;
wire [`numNeuronLayer1-1:0] o1_valid;
wire [`numNeuronLayer1*`dataWidth-1:0] x1_out;
reg [`numNeuronLayer1*`dataWidth-1:0] holdData_1;
reg [`dataWidth-1:0] out_data_1;
reg data_out_valid_1;
if(neuron_valid11==1&&neuron_valid12==1&&neuron_valid13==1&&neuron_valid14==0&&neuron_valid15==1&&neuron_valid16==0&&neuron_valid17==0&&neuron_valid18==0)begin
Layer_1 #(.NN(`numNeuronLayer1),.numWeight(`numWeightLayer1),.dataWidth(`dataWidth),.layerNum(1),.sigmoidSize(`sigmoidSize),.weightIntWidth(`weightIntWidth),.actType(`Layer1ActType)) l1(
.ActiveN1(1),
.ActiveN2(1),
.ActiveN3(1),
.ActiveN4(0),
.ActiveN5(1),
.ActiveN6(0),
.ActiveN7(0),
.ActiveN8(0),
.clk(s_axi_aclk),
.rst(reset),
.weightValue(weightValue),
.biasValue(biasValue),
.sensor1(sensor1),
.sensor2(sensor2),
.sensor3(sensor3),
.sensor4(sensor4),
.sensor5(sensor5),
.sensor6(sensor6),
.o_valid(o1_valid),
.x_out(x1_out)
);
end
What you have written is
// If a wire equals 1
if(neuron_valid11==1...)begin
// Declare a module instance
Layer_1 #(..)(...);
end
You can't say 'while the design is running, if this wire has a certain value==1 then these modules exist in my design' - doesn't make sense. The module is a physical thing, fixed there or not, not popping in and out of existence.
You can at compile time do 'if MY_PARAM=SOMETHING begin, then instantiate your module' as long as the value is constant (as your error says). See https://www.chipverify.com/verilog/verilog-generate-block.
Or perhaps you want to select/mux signals into your module (maybe you want it disconnected/disabled sometimes and not others based on some condition). You would do that inside a always block, ex. checking if(neuron_valid11==1 and driving signals that connect to your (always-existing) module instance. https://www.chipverify.com/verilog/verilog-4to1-mux
I want to use SW[15] to switch between module A_7seg and B_7seg but it does not work. (2 modules work separately)
module mix(input CLOCK,input [15:0]SW,output reg [15:0] led,output [3:0] an,output reg[7:0] seg);
generate
case(SW[15])
1'b0:A_7seg (.CLOCK(CLOCK),.an(an),.seg(seg));
1'b1:B_7seg (.CLOCK(CLOCK),.SW(SW),.led(led),.an(an),.seg(seg));
endcase
endgenerate
endmodule
Since '2 modules work separately', the simple way is to use SW[15] to select between 2 modules' outputs.
module mix(
input CLOCK,
input [15:0] SW,
output reg [15:0] led,
output reg [3:0] an,
output reg [7:0] seg
);
wire [15:0] B_led;
wire [3:0] A_an, B_an;
wire [7:0] A_seg, B_seg;
// if not using 'generate' block, modules are instantiated at
// the top level, not in other 'if'/'case'/... structures.
// and name the 2 instantiations
A_7seg u_A_7seg (.CLOCK(CLOCK), .an(A_an), .seg(A_seg));
B_7seg u_B_7seg (.CLOCK(CLOCK), .SW(SW), .led(B_led), .an(B_an), .seg(B_seg));
// this extra circuit is needed to select between the two
always#(*)begin
if(SW[15])begin
led = B_led;
an = B_an;
seg = B_seg;
end
else begin
led = 16'h0; // <-- I assume the inactive value for 'led' is all-zero
an = A_an;
seg = A_seg;
end
end
endmodule
You may also want to use SW[15] to gate the inputs to the one that is not currently working to reduce power consumption.
You need to figure out the schematic before you understand how to write the code.
Lets say I have a Verilog module with bit vector ports. How do I
instantiate it with some bits left unconnected?
I tried something like this but it didn't work:
module sub (in,out)
input [3:0] in;
output [3:0] out;
endmodule
module top;
wire [1:0] a1;
wire [1:0] c1;
sub Sub1(
.in[2:1](a1[1:0]),
.out[2:1](c1[1:0])
);
endomdule
It would be much easier to just declare signals of the correct size and use a continuous assignment
module top;
wire [1:0] a1;
wire [1:0] c1;
wire [3:0] pin;
wire [3:0] pout;
assign pin[2:1] = a1;
assign c1 = pout[2:1];
sub Sub1(
.in(pin),
.out(pout)
);
endomdule
In general, it is not a good idea to leave input ports floating. You could use a concatenation in the assignment, or directly in the port connection.
sub Sub1(
.in({1'b0,a1,1'b0}),
.out({pout[3],c1,pout[0]})
);
SystemVerilog has a net aliasing construct that makes thing even simpler
module top;
wire [3:0] pin;
wire [3:0] pout;
alias pin[2:1] = a1;
alias pout[2:1] = c1;
sub Sub1(
.in(pin),
.out(pout)
);
endomdule
Found LRM reference on why you cannot connect parts of ports.
LRM 1800-2012 Section 23.3.2.2 Connecting module instance ports by name:
The port_name shall be the name specified in the module declaration. The port name cannot be a bit-select, a part-select, or a concatenation of ports.
you cannot connect/disconnect parts of a port. You can do it with the whole port though. so, in your case you nedd to split your port in several parts, something like the following:
module sub (in1, in2, out1, out2);
input [2:1] in1;
input [1:0] in2;
output [2:1] out1;
output [1:0] out2;
endmodule
module top;
wire [1:0] a1;
wire [1:0] c1;
sub Sub1(
.in1(a1[1:0]),
.in2(),
.out1(c1[1:0]),
.out2()
);
endmodule
My code connect 4-bits to module's 8-bit outputs, upper/lower even middle part.
It does work, but what the hell is the 's'(or anything)?
It works in both Quartus Prime 18.0pro and Lattice Diamond 3.10(Symplify Pro).
module dff8
(
input clk,
input [7:0] a,
output reg [7:0] b
);
always # (posedge clk) begin
b <= a;
end
endmodule
module top
(
input clk,
input [7:0] x,
output [3:0] y,
output [3:0] z
);
dff8 u0 (.clk(clk), .a(x), .b({y,s,s,s,s}));
dff8 u1 (.clk(clk), .a(x), .b({s,s,s,s,z}));
endmodule
PS_GPIO is a 56 bits "inout" signal in module "xillydemo". Now I want to assign different part of PS_GPIO to three different port in top module:
module xilly_mydemo(
input clk_100,
input otg_oc,
inout [23:0] PS_GPIO1,
output [23:0] PS_GPIO2,
input [7:0] PS_GPIO3,
output [3:0] GPIO_LED,
output [3:0] vga4_blue,
output [3:0] vga4_green,
output [3:0] vga4_red,
output vga_hsync,
output vga_vsync,
output audio_mclk,
output audio_dac,
input audio_adc,
input audio_bclk,
input audio_lrclk,
output smb_sclk,
inout smb_sdata,
output [1:0] smbus_addr,
output [23:0] sig_out);
wire [23:0]PS_GPIO1;
wire [23:0]PS_GPIO2;
wire [7:0] PS_GPIO3;
xillydemo xillydemo(
.clk_100(clk_100),
.otg_oc(otg_oc),
.PS_GPIO(PS_GPIO),
.GPIO_LED(GPIO_LED),
.vga4_blue(vga4_blue),
.vga4_green(vga4_green),
.vga4_red(vga4_red),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.audio_mclk(audio_mclk),
.audio_dac(audio_dac),
.audio_adc(audio_adc),
.audio_bclk(audio_bclk),
.audio_lrclk(audio_lrclk),
.smb_sclk(smb_sclk),
.smb_sdata(smb_sdata),
.smbus_addr(smbus_addr),
.sig_out(sig_out)
);
assign PS_GPIO1 = PS_GPIO[23:0];
assign PS_GPIO2= PS_GPIO[24:47];
assign PS_GPIO3=PS_GPIO[48:55];
endmodule
But it shows "cannot index into non-array type wire for PS_GPIO".
Can anyone help me out?
Thanks!
You have not defined PS_GPIO anywhere so Verilog assumes a single bit.
Even if that is fixed, I don't think you are on the right track.
Messing about with inout and splitting it in input, output and inout ports is at least confusing. I am not even sure the tool will accept it as written there.
Make a clean design, make three ports in xillydemo one input, one output and one inout all of the correct width.
I'm trying to implement a simple verilog code as below:
module test1(
input ACLK,
input RST,
output test_output1,
output test_output2
);
//wire ACLK;
//wire RST;
reg test_output1;
reg test_output2;
assign test_output1 = ACLK;
always #(posedge ACLK or negedge RST)
begin
if(!RST)
begin
//test_output1 <=0;
test_output2 <=0;
end
else
begin
//test_output1 <=0;
test_output2 <=1;
end
end
endmodule
I get the following error message when I try to synthesize it in Xilinx ISE:
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "test1.v" in library work
ERROR:HDLCompilers:27 - "test1.v" line 30 Illegal redeclaration of 'test_output1'
ERROR:HDLCompilers:27 - "test1.v" line 31 Illegal redeclaration of 'test_output2`
I am unable to resolve this error. Any help would be highly appreciated.
If you declare the directional of the port in the portlist, you must also declare the type. This is referred to as an ANSI style header.
There is also a non-ANSI style header that separates the portlist, directional, and type. If you are fallowing IEEE1364-1995 convention then you must use non-ANSI style and you cannot declare the type (e.g. output reg test_output2; is illegal, while output test_output2; reg test_output2; is legal). Since IEEE1364-2001 ANSI and non-ANSI style is supported (and the non-ANSI allows output reg test_output2;). All modern Verilog simulators are SystemVerilog (IEEE1800) simulators, therefore it is the designers choice. (ANSI style is more popular as it is less typing).
ANSI style header:
module test1(
input ACLK,
input RST,
output test_output1,
output reg test_output2 );
Non-ANSI style header:
module test1( ACLK, RST, test_output1, test_output2 );
input ACLK;
input RST;
output test_output1;
output test_output2;
reg test_output2;
Note: With IEEE1364, you can not drive a reg with an assign statement, it must be a net type. IEEE1800 has softened the rule the it is recommenced logic in stead of reg, but generally if you are going to use assign then you should be assigning a net (e.g. wire).
Add following modification:
You used test_output1 in assign statement so it should be of type wire.
module test1(
input wire ACLK,
input wire RST,
output wire test_output1,
output reg test_output2
);
You have already declared test_output1 and test_outpu2 as output and it is by default of type wire, so you just have to implicitly specify wire or reg according to usage,
// reg test_output1;
// reg test_output2;