PS_GPIO is a 56 bits "inout" signal in module "xillydemo". Now I want to assign different part of PS_GPIO to three different port in top module:
module xilly_mydemo(
input clk_100,
input otg_oc,
inout [23:0] PS_GPIO1,
output [23:0] PS_GPIO2,
input [7:0] PS_GPIO3,
output [3:0] GPIO_LED,
output [3:0] vga4_blue,
output [3:0] vga4_green,
output [3:0] vga4_red,
output vga_hsync,
output vga_vsync,
output audio_mclk,
output audio_dac,
input audio_adc,
input audio_bclk,
input audio_lrclk,
output smb_sclk,
inout smb_sdata,
output [1:0] smbus_addr,
output [23:0] sig_out);
wire [23:0]PS_GPIO1;
wire [23:0]PS_GPIO2;
wire [7:0] PS_GPIO3;
xillydemo xillydemo(
.clk_100(clk_100),
.otg_oc(otg_oc),
.PS_GPIO(PS_GPIO),
.GPIO_LED(GPIO_LED),
.vga4_blue(vga4_blue),
.vga4_green(vga4_green),
.vga4_red(vga4_red),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.audio_mclk(audio_mclk),
.audio_dac(audio_dac),
.audio_adc(audio_adc),
.audio_bclk(audio_bclk),
.audio_lrclk(audio_lrclk),
.smb_sclk(smb_sclk),
.smb_sdata(smb_sdata),
.smbus_addr(smbus_addr),
.sig_out(sig_out)
);
assign PS_GPIO1 = PS_GPIO[23:0];
assign PS_GPIO2= PS_GPIO[24:47];
assign PS_GPIO3=PS_GPIO[48:55];
endmodule
But it shows "cannot index into non-array type wire for PS_GPIO".
Can anyone help me out?
Thanks!
You have not defined PS_GPIO anywhere so Verilog assumes a single bit.
Even if that is fixed, I don't think you are on the right track.
Messing about with inout and splitting it in input, output and inout ports is at least confusing. I am not even sure the tool will accept it as written there.
Make a clean design, make three ports in xillydemo one input, one output and one inout all of the correct width.
Related
I am trying to instantiate modules inside various if else statements but i am getting the error with the first argument in the if parenthesis "signal is not a constant".All my arguments in the parenthesis of my if and if else statements are input wires,and i can't figure whats wrong
Thanks
I've tried passing the signals from a matrix to a single input for each position of the matrix but that didn't work either
Heres my some of my code below
The error is as follows:[Synth 8-35] 'neuron_valid11' is not a constant
`include "include.v"
module FeedForward(
//Input
input wire[`dataWidth-1:0] sensor1,
input wire[`dataWidth-1:0] sensor2,
input wire[`dataWidth-1:0] sensor3,
input wire[`dataWidth-1:0] sensor4,
input wire[`dataWidth-1:0] sensor5,
input wire[`dataWidth-1:0] sensor6,
input wire neuron_valid11,
input wire neuron_valid12,
input wire neuron_valid13,
input wire neuron_valid14,
input wire neuron_valid15,
input wire neuron_valid16,
input wire neuron_valid17,
input wire neuron_valid18,
input wire neuron_valid21,
input wire neuron_valid22,
input wire neuron_valid23,
input wire neuron_valid24,
input wire neuron_valid25,
input wire neuron_valid26,
input wire neuron_valid27,
input wire neuron_valid28,
input wire[(`dataWidth/2)-1:0] targetVals
);
wire [7:0] weightValue;
wire [7:0] biasValue;
wire [7:0] out;
integer Loop;
wire ActiveN1;
wire ActiveN2;
wire ActiveN3;
wire ActiveN4;
wire ActiveN5;
wire ActiveN6;
wire ActiveN7;
wire ActiveN8;
wire reset;
localparam IDLE = 'd0,
SEND = 'd1;
wire [`numNeuronLayer1-1:0] o1_valid;
wire [`numNeuronLayer1*`dataWidth-1:0] x1_out;
reg [`numNeuronLayer1*`dataWidth-1:0] holdData_1;
reg [`dataWidth-1:0] out_data_1;
reg data_out_valid_1;
if(neuron_valid11==1&&neuron_valid12==1&&neuron_valid13==1&&neuron_valid14==0&&neuron_valid15==1&&neuron_valid16==0&&neuron_valid17==0&&neuron_valid18==0)begin
Layer_1 #(.NN(`numNeuronLayer1),.numWeight(`numWeightLayer1),.dataWidth(`dataWidth),.layerNum(1),.sigmoidSize(`sigmoidSize),.weightIntWidth(`weightIntWidth),.actType(`Layer1ActType)) l1(
.ActiveN1(1),
.ActiveN2(1),
.ActiveN3(1),
.ActiveN4(0),
.ActiveN5(1),
.ActiveN6(0),
.ActiveN7(0),
.ActiveN8(0),
.clk(s_axi_aclk),
.rst(reset),
.weightValue(weightValue),
.biasValue(biasValue),
.sensor1(sensor1),
.sensor2(sensor2),
.sensor3(sensor3),
.sensor4(sensor4),
.sensor5(sensor5),
.sensor6(sensor6),
.o_valid(o1_valid),
.x_out(x1_out)
);
end
What you have written is
// If a wire equals 1
if(neuron_valid11==1...)begin
// Declare a module instance
Layer_1 #(..)(...);
end
You can't say 'while the design is running, if this wire has a certain value==1 then these modules exist in my design' - doesn't make sense. The module is a physical thing, fixed there or not, not popping in and out of existence.
You can at compile time do 'if MY_PARAM=SOMETHING begin, then instantiate your module' as long as the value is constant (as your error says). See https://www.chipverify.com/verilog/verilog-generate-block.
Or perhaps you want to select/mux signals into your module (maybe you want it disconnected/disabled sometimes and not others based on some condition). You would do that inside a always block, ex. checking if(neuron_valid11==1 and driving signals that connect to your (always-existing) module instance. https://www.chipverify.com/verilog/verilog-4to1-mux
The following code will not build exiting with Error Code -6
module and_gate (
input [1:0] io_button,
output [2:0] io_led
);
wire wire1;
assign wire1 = io_button[0];
assign io_led[0] = wire1;
endmodule
But making this small change builds properly. Can you not just assign a wire to an output without modifying it in some way?
module and_gate (
input [1:0] io_button,
output [2:0] io_led
);
wire wire1;
assign wire1 = io_button[0];
assign io_led[0] = ~wire1;
endmodule
I've seen this before. Some synthesis tools don't handle well the case of there being zero gates in the design, as that means there's zero die area needed before routing. I'm guessing the tool is hitting some internal divide-by-0.
So yes, you can simply connect a wire to an output. That by itself is perfectly valid. And you can even connect an input directly to an output. As long as you have any other gates in the design, even unrelated/unconnected to the ports/nets in your example, the synthesizer would be happy, as there'd be non-zero die area.
So I bet this would work fine:
module and_gate (
input [1:0] io_button,
output [2:0] io_led
);
wire wire1;
assign wire1 = io_button[0];
assign io_led[0] = wire1;
assign io_led[1] = ~io_button[1]; // added line, just to infer a gate somewhere
endmodule
I'm running into the following errors when trying to synthesize my code to run on my Anvyl board:
ERROR:HDLCompiler:329 - "C:/Users/Chase/Desktop/Code
Templates/final_bcd_counter.v" Line 25: Target <digit_1> of concurrent assignment or output port connection should be a net type.
ERROR:HDLCompiler:329 - "C:/Users/Chase/Desktop/Code
Templates/final_bcd_counter.v" Line 26: Target <digit_2> of concurrent assignment or output port connection should be a net type.
I was provided with a Lab_board.v file to drive the board which is as follows:
`timescale 1ns / 1ps
module lab_board(LED, SW, CLK);
output [7:0] LED;
input [7:0] SW;
input CLK;
bcd_count_7 counter(
.max_count(SW[6:0]),
.CLK(CLK),
.run(SW[7]),
.digit_l(LED[3:0]),
.digit_2(LED[7:4])
);
endmodule
The code that the errors are throw in is my final_bcd_counter.v file which is the main driver of the program that passes all the needed values to the board. It is as follows:
// This is the top module for the programmable BCD counter.
// It implements a programmable 7-bit counter and a binary-
// to-bcd converter that can output two digits.
module bcd_count_7(max_count, CLK, run, digit_1, digit_2);
input [6:0] max_count;
input CLK, run;
output reg [3:0] digit_1;
output reg [3:0] digit_2;
//Wires and registers for interconnect if needed
wire [6:0] countin_out;
// Programmable 7-bit counter module
prog_count_7 counter(.max_count(max_count),
.run(run),
.CLK(CLK),
.count_out(countin_out));
// Binary-to-BCD Converter for converting count_out to BCD
binary_bcd_2 bcd_converter(.bin_in(countin_out),
.digit_1(digit_1),
.digit_2(digit_2));
endmodule
I've tried changing the type of digit_1 and digit_2 with no avail. Could the solution be creating wires that connect to the lab board instead of passing output registers, if so, what would that look like?
Any help is appreciated. I can provide the code of the other modules in the program if needed.
Thanks!
You've declared digit_1/2 as a variable and it needs to be a net in Verilog I'm assuming those are output ports from your binary_bcd_2 module. SystemVerilog does not have this restriction.
Simply remove the reg keyword from the port declaration. I've added wire for clarity, but that is what is implicit
module bcd_count_7(
input wire [6:0] max_count,
input wire CLK, run,
output wire [3:0] digit_1,
output wire [3:0] digit_2
);
My goal is to form this code with Quartus, but the problem is I don't know how to fix the problem.
I've tried to know what Error 10028 means, but I cant figure out how to work with it.
Can someone teach me how to fix it or if there's a way to bypass it?
module mem (r_wb,addr,d,q);
input r_wb;//0write 1read
input [7:0] addr;
input [7:0 ] d;
output [7:0] q;
reg [7:0] q;
reg [7:0] mem_bank [0:255];
always #(r_wb)
if (r_wb) q=mem_bank[addr];
else mem_bank[addr]=d;
always #(addr)
if (r_wb) q=mem_bank[addr];
else mem_bank[addr]=d;
always #(d)
if (r_wb) q=mem_bank[addr];
else mem_bank[addr]=d;
endmodule
The code you put in your comment is mostly correct in the fact that you do need a clocking signal. However you should be using non-blocking assignment (<=).
I would recommend changing your model header to ANSI style which has been around since 2001. The non-ANSI style required q the be identified three times; port list, direction, type. ANSI style compacts it. Non-ANSI is good to understand because a lot of synthesizers and code generators still use it by default. But any modern simulator or synthesizer will accept ANSI style as input.
module mem (
input clk,
input r_wb, //0write 1read
input [7:0] addr,
input [7:0 ] d,
output reg [7:0] q) ;
reg [7:0] mem_bank [0:255];
always #(posedge clk)
if (r_wb) q<=mem_bank[addr];
else mem_bank[addr]<=d;
endmodule
For the record, I'm a complete Verilog newbie. I'm writing a module that uses a few bidirectional buses.
inout wire [KEY_SIZE-1:0] prevKey;
inout wire [TAG_SIZE-1:0] prevTag;
inout wire [KEY_SIZE-1:0] nextKey;
inout wire [TAG_SIZE-1:0] nextTag;
I know how I read things off of the bus, but how do I write something onto it? If I use an assign statement to a reg, will the value of the reg get clobbered when new data comes onto the wire? Is dealing with an inout port worth the hassle, or should I just make an input and and output bus for each?
If I use an assign statement to a reg...
This statement doesn't really make sense, you don't do assignments to regs, you do assignments to wires.
Simple example of driving an inout wire:
inout wire bidir_wire;
reg drive_value;
reg drive_enable;
reg something;
assign bidir_wire = drive_enable ? drive_value : 1'bz;
always #(posedge clk) begin
drive_value <= ... ; //assign a drive value based on some criteria
drive_enable <= ...;
something <= bidir_wire; //do something with the input value
end