The value of oV should be the value on the right side in the StateToCountSequence that corresponds to the respective iState value on the left. However, oV only seems to be able to have the values 2 or 3, as shown the in capture below.
Does anyone know what I should do about this?
module CounterSkipReverse(iClk, iRst, iSkip, iRev, oState);
input iClk, iRst, iSkip, iRev;
//declare oState:
output integer oState;
//declare internal wires and reg types here:
always # (posedge iClk) begin
if (iRst == 1)
oState <= 0;
else
if (iSkip == 0 & iRev == 0) oState <= oState + 4'd1;
else if (iSkip == 1 & iRev == 0) oState <= oState + 4'd5;
else if (iSkip == 0 & iRev == 1) oState <= oState - 4'd1;
else if (iSkip == 1 & iRev == 1) oState <= oState + 4'd9;
if (oState < 0) oState <= oState + 4'd14;
if (oState > 14) oState <= oState - 4'd14;
end
endmodule
module StateToCountSequence(iState, oV);
//declare the input and output
input iState;
output reg [3:0]oV;
//declare any internal wire and reg types here.
always # (iState) begin
case(iState)
4'd0: oV = 4'd3;
4'd1: oV = 4'd2;
4'd2: oV = 4'd4;
4'd3: oV = 4'd9;
4'd4: oV = 4'd9;
4'd5: oV = 4'd0;
4'd6: oV = 4'd7;
4'd7: oV = 4'd1;
4'd8: oV = 4'd1;
4'd9: oV = 4'd5;
4'd10: oV = 4'd1;
4'd11: oV = 4'd7;
4'd12: oV = 4'd0;
4'd13: oV = 4'd8;
4'd14: oV = 4'd9;
endcase
end
//Have you checked for inferred latches in this module?
endmodule
module CompleteCounter(iClk, iRst, iSkip, iRev, oV, oState);
input iClk, iRst, iSkip, iRev;
output [3:0] oV;
//declare oState next line
output [3:0]oState;
CounterSkipReverse cntr(.iClk(iClk), .iRst(iRst), .iSkip(iSkip), .iRev(iRev), .oState(oState));
StateToCountSequence statemap(.iState(oState), .oV(oV));
endmodule
`timescale 1ns / 1ps
module AssignmentTestBench;
//declare internal signals and instantiate module CompleteCounter.
reg iClk, iRst, iSkip, iRev;
wire [3:0]oState;
wire [3:0]oV;
initial begin
iClk = 1'b1;
iRst = 0;
iSkip = 0;
iRev = 0;
end
CompleteCounter counter(iClk, iRst, iSkip, iRev, oV, oState);
//generate test sequences for all state transitions
always begin
#5 iClk = ~iClk; //period 10 ns for clock
end
always begin // control w input and reset
#1;
// iSkip = 0, iRev = 0
#10 iRst = 1'b1;
#10 iRst = 1'b0;
#300; // 30 clock cycles
// iSkip = 1, iRev = 0
#10 iRst = 1'b1;
#10 iRst = 1'b0;
iSkip = 1'b1;
#80;
// iSkip = 1, iRev = 1
#10 iRst = 1'b1;
#10 iRst = 1'b0;
iRev = 1'b1;
#40;
// iSkip = 0, iRev = 1
#10 iRst = 1'b1;
#10 iRst = 1'b0;
iSkip = 1'b0;
#150;
$display("Finished test");
$finish; // remove for modelsim
$stop;
end
endmodule
The signal iState is a 1-bit signal in the StateToCountSequence, which means it can only take on the known values 0 and 1. Thus, you can only set oV to 3 and 2.
Change:
input iState;
to:
input [3:0] iState;
Related
For a lab I must create the logic to use on a Digilent PMOD ALS. In the lab requirenment I cannot use the sclk signal on the sensitivity list and therefore use a state machine to create the 2.5 MHz clk signal to send to the PMOD ALS. See the code below:
module sens_interface(
input clk, //clk 10Mhz
input reset_n,
input [15:0] delay,
input datain,
output reg sclk,
output reg cs_n,
output reg [3:0] Cout,
output reg [3:0] Dout,
output reg [5:0] cnt
);
//params
//state machine 1
parameter SA0 = 3'b000;
parameter SA1 = 3'b001;
parameter SA2 = 3'b010;
parameter SA3 = 3'b011;
parameter SD0 = 3'b100;
parameter SD1 = 3'b101;
//state machine 2
parameter SR0 = 2'b00;
parameter SR1 = 2'b01;
parameter SR2 = 2'b10;
parameter SR3 = 2'b11;
//pmod als registers
//reg sclk; //2.5Mhz clk
//reg cs_n; //
reg [14:0] data_reg;
//count registers
//reg [5:0] cnt;
reg [15:0] cnt_d;
reg [5:0] cnt_r;
//state registers
reg [2:0] state_sclk;
reg [1:0] state_data;
//State Machine 1
always # (posedge clk)begin
if(reset_n == 1'b0)begin
cs_n <= 1'b1;
sclk <= 0;
cnt <= 6'd0;
cnt_d <= 16'd0;
end
else
case(state_sclk)
SA0:begin
sclk <= 1'b1;
state_sclk <= SA1;
if (cnt <= 6'd17)
cs_n <= 1'b0;
else
cs_n <= 1'b1;
end
SA1:begin
state_sclk <= SA2;
end
SA2:begin
sclk <= 1'b0;
cnt <= cnt + 1;
state_sclk <= SA3;
end
SA3:begin
if(cnt == 6'd21)begin
cnt <= 0;
state_sclk <= SD0;
end
else
state_sclk <= SA0;
end
SD0:begin
cnt_d <= delay;
state_sclk <= SD1;
end
SD1:begin
if (cnt_d == 0)
state_sclk <= SA0;
else
cnt_d <= cnt_d - 1;
end
default:begin
state_sclk <= SA0;
end
endcase
end
always # (posedge clk)begin
if (reset_n == 1'b0)begin
cnt_r <= 0;
data_reg <= 0;
end
else begin
case (state_data)
SR0:begin
if (cs_n == 1'b1 && sclk == 1'b1)
state_data <= SR1;
end
SR1: begin
if (cs_n == 1'b1)begin
state_data <= SR0;
cnt_r <= 0;
end
else if (sclk == 1'b0)
state_data <= SR2;
end
SR2:begin
if (cs_n == 1'b1)begin
state_data <= SR0;
cnt_r <= 0;
end
else if (cnt_r == 15)
state_data <= SR3;
else if (sclk == 1'b1)begin
data_reg [14-cnt_r] <= datain;
cnt_r <= cnt_r + 1;
state_data <= SR1;
end
end
SR3:begin
if (cs_n == 1) begin
Cout <= data_reg [11:8];
Dout <= data_reg [7:4];
state_data <= SR0;
end
end
default:begin
state_data <= SR0;
end
endcase
end
end
endmodule
I tried to make a simulation of it and the simulation indicates that after my cnt register reaches 15 it just cuts out and goes to 0.
simulation
That behavior is caused by your SA3 state.
SA3:begin
if(cnt == 6'd21)begin
cnt <= 0;
state_sclk <= SD0;
end
else
state_sclk <= SA0;
end
end
When your cnt == 6'd21 (which is 6'h15) the cnt is set to zero.
The generic variable names and lack of comments makes it difficult to see why this is not the expected behavior.
I want iState (the 2nd bar from the bottom) to be 0 on the rising edge of the clock (the bar at the very top) and when its current value is 1110 (provided that iSkip and iRev are both 0) or when 1010 (provided that iSkip is 1 and iRev are both 0). However, its going to 1111 instead. Does anyone know why this is happening and what I should do about it? Thanks.
Does anyone know what I should do about this? Thanks.
module CounterSkipReverse(iClk, iRst, iSkip, iRev, oState);
input iClk, iRst, iSkip, iRev;
//declare oState:
output integer oState;
//declare internal wires and reg types here:
always # (posedge iClk) begin
if (iRst == 1)
oState <= 0;
else
if (iSkip == 0 & iRev == 0) oState <= oState + 4'd1;
else if (iSkip == 1 & iRev == 0) oState <= oState + 4'd5;
else if (iSkip == 0 & iRev == 1) oState <= oState - 4'd1;
else if (iSkip == 1 & iRev == 1) oState <= oState + 4'd9;
if (oState < 0) oState <= oState + 4'd14;
if (oState > 14) oState <= oState - 4'd14;
end
endmodule
module StateToCountSequence(iState, oV);
//declare the input and output
input iState;
output reg [3:0]oV;
//declare any internal wire and reg types here.
always # (iState) begin
case(iState)
4'd0: oV = 4'd3;
4'd1: oV = 4'd2;
4'd2: oV = 4'd4;
4'd3: oV = 4'd9;
4'd4: oV = 4'd9;
4'd5: oV = 4'd0;
4'd6: oV = 4'd7;
4'd7: oV = 4'd1;
4'd8: oV = 4'd1;
4'd9: oV = 4'd5;
4'd10: oV = 4'd1;
4'd11: oV = 4'd7;
4'd12: oV = 4'd0;
4'd13: oV = 4'd8;
4'd14: oV = 4'd9;
endcase
end
//Have you checked for inferred latches in this module?
endmodule
module CompleteCounter(iClk, iRst, iSkip, iRev, oV, oState);
input iClk, iRst, iSkip, iRev;
output [3:0] oV;
//declare oState next line
output [3:0]oState;
CounterSkipReverse cntr(.iClk(iClk), .iRst(iRst), .iSkip(iSkip), .iRev(iRev), .oState(oState));
StateToCountSequence statemap(.iState(oState), .oV(oV));
endmodule
`timescale 1ns / 1ps
module AssignmentTestBench;
//declare internal signals and instantiate module CompleteCounter.
reg iClk, iRst, iSkip, iRev;
wire [3:0]oState;
wire [3:0]oV;
initial begin
iClk = 1'b1;
iRst = 0;
iSkip = 0;
iRev = 0;
end
CompleteCounter counter(iClk, iRst, iSkip, iRev, oV, oState);
//generate test sequences for all state transitions
always begin
#5 iClk = ~iClk; //period 10 ns for clock
end
always begin // control w input and reset
#1;
// iSkip = 0, iRev = 0
#10 iRst = 1'b1;
#10 iRst = 1'b0;
#300; // 30 clock cycles
// iSkip = 1, iRev = 0
#10 iRst = 1'b1;
#10 iRst = 1'b0;
iSkip = 1'b1;
#80;
// iSkip = 1, iRev = 1
#10 iRst = 1'b1;
#10 iRst = 1'b0;
iRev = 1'b1;
#40;
// iSkip = 0, iRev = 1
#10 iRst = 1'b1;
#10 iRst = 1'b0;
iSkip = 1'b0;
#150;
$display("Finished test");
$finish; // remove for modelsim
$stop;
end
endmodule
The way the <= work is to assign the value to the oState later, after the block is done. So, in the following while oState is scheduled to be 15, the if statement still sees it as 14.
oState <= oState + 1;
...
if (oState > 14) ...
As minimum, you need if(oState >= 14);
also, in the following statement
if (oState > 14) oState <= oState - 4'd14;
if oState is really bigger than 14, i.e. 15, then 15 - 14 = 1;
you probably need
if (oState > 14) oState <= 0;
You need to figure out the other side of the expression as well. The problem is that if (oState <= 0) will give you a trouble in combination with ostate <= 0. You probably need something like the following there: if (iSkip == 0 && iRev == 1 && oState <= 0)
A few more issues:
BToState is integer in CounterSkipReverse which is 32 bit wide signed. istate on the other hand is a one-bit wide input in StateToCountSequence. You need to make all of them of the same width. Your case statement will not work with 1-bit iState.
In addition, do not use singel & in conditional statements. use `&&. Though it does not matter in your case, it really matters in my suggestion which i provided above.
Do not use always #(iState), use always #*.
I have made a bit error rate (ber) file in verilog. In ber module, I have made total_error which compares the t_data and rx_data and totals up the number of errors it gets from comparing.
Here is the code
`timescale 1ns / 1ps
module ber
(
clk,
rstn,
T_Data,
RX_Data,
total_error,
enable
);
//inputs
input clk;
input rstn;
input [15 : 0] T_Data;
input [15 : 0] RX_Data;
input enable;
//outputs
output [15:0] total_error;
reg [4:0] i;
reg [15:0] subtotal, next_subtotal;
assign total_error = subtotal;
always #(posedge clk) begin : comb
next_subtotal = 0;
for (i = 0; i < 16; i = i + 1)
begin
if (T_Data[i] != RX_Data[i] )
begin
next_subtotal = next_subtotal + 1;
end
end
end
always #(posedge clk) begin : dff
if (rstn==1'b0)
begin
subtotal <= 7'b0000000;
end else
begin
subtotal <= next_subtotal;
end
end
endmodule
After making the BER file, I made another file known as BER_STATE_MACHINE where I made a state machine for TRANFERRING AND RECEIVING SIGNALS, I instantiated the ber file with this ber_state_machine file.
Here is the code
// --------------------------------------------------------------------
`timescale 1ns/1ps
module ber_state_machine
(
clk,
resetn,
T_Data [15:0],
T_Valid,
T_Ready,
RX_Data [15:0],
RX_Active,
RX_Valid,
total_error
);
//-----------------------------------
input resetn, clk;
// DECLARING INPUTS AND OUTPUTS FOR TRASMIT SIGNALS
input [15 : 0] T_Data;
input T_Valid;
output T_Ready;
// DECLARING INPUTS AND OUTPUTS FOR RECEIVING SIGNALS
input [15 : 0] RX_Data;
input RX_Active;
input RX_Valid;
//-----------------------------------
output [15 : 0] total_error;
//-----------------------------------
reg [6:0] sel;
reg execute_in;
reg T_Ready;
//------------------------------------------
ber uut
(
.clk(clk),
.rstn(resetn),
.T_Data(T_Data),
.RX_Data(RX_Data),
.total_error(total_error),
.enable(execute_in)
);
//------------------------------------------
// MAKING STATE MACHINE HERE //INPUTS
always # (posedge clk or negedge resetn) // state machine for changing states
begin
if (resetn == 1'b1) // idle state
begin
sel <= 7'b000; // state 0
end
else if (T_Valid == 7'b1)
begin
sel <= 7'b001; // state 1
end
else if (sel == 7'b001)
begin
sel <= 7'b010; // state 2
end
else if (RX_Active == 7'b1)
begin
sel <= 7'b011; // state 3
end
else if (T_Valid == 7'b1 && RX_Valid == 7'b1)
begin
sel <= 7'b100; // state 4
end
else if (sel == 7'b100)
begin
sel <= 7'b101; // state 5
end
else if (T_Valid == 2'b0 && RX_Valid == 2'b0)
begin
sel <= 7'b100; // going back to state 4
end
end
// STATE MACHINE //OUTPUTS
always # (posedge clk) // outputs for every state in state diagram
begin
case(sel)
7'b000 :
execute_in = 2'b0; // state 0
7'b001 :
T_Ready = 2'b1; // state 1
7'b010 :
T_Ready = 2'b0; // state 2
7'b011 :
execute_in = 2'b1; // state 3
7'b100 :
T_Ready = 2'b1; // state 4
7'b101 :
T_Ready = 2'b0; // state 5
endcase
end
endmodule
After this, I made a test bech to see the behavioral simulation.
There are few problems that I am getting which I am not able to fix due to less verilog experience.
the t_data and rx_data are undefined in the simulation, after the last bit, I can see the value each contains but from 0 - 15, they are undefined. I really dont know whats the problem.
I dont see any value in total_error, even though I put errors in t_data and rx_data but I dont see the number of errors in total_error. But I can observe in the simulation that there are errors in t_data and rx_data in their final values.
Here is the code for test bench
`timescale 1ns / 1ps
module test_bench();
//inputs
reg execute_in;
reg clk;
reg resetn;
//inputs for transferring signals
reg [15:0] T_Data;
reg T_Valid;
//inputs for receiving signals
reg [15:0] RX_Data;
reg RX_Active;
reg RX_Valid;
//outputs
wire [15:0] total_error;
wire T_Ready;
//instantiate the unit under test (UUT)
ber_state_machine uut_ber
(
.clk(clk),
.resetn(resetn),
.T_Data(T_Data),
.T_Valid(T_Valid),
.T_Ready(T_Ready),
.RX_Data(RX_Data),
.RX_Active(RX_Active),
.RX_Valid(RX_Valid),
.total_error(total_error)
);
initial begin
clk = 1'b0;
resetn = 1'b1;
repeat(4) #10 clk = ~clk;
resetn = 1'b0;
forever #10 clk = ~clk;
end
initial begin
#100
execute_in = 0;
#100
execute_in = 1;
#100
T_Valid = 1'b0;
RX_Active = 1'b0;
#100
RX_Valid = 1'b0;
//************//
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[0] = 1'b0; // data 0 // make it 0 for error
RX_Valid = 1'b1;
RX_Data[0] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
//************//
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[1] = 1'b1; // data 1
RX_Valid = 1'b1;
RX_Data[1] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[2] = 1'b1; // data 2
RX_Valid = 1'b1;
RX_Data[2] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[3] = 1'b0; // data 3
RX_Valid = 1'b1;
RX_Data[3] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[4] = 1'b1; // data 4
RX_Valid = 1'b1;
RX_Data[4] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[5] = 1'b1; // data 5
RX_Valid = 1'b1;
RX_Data[5] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[6] = 1'b1; // data 6
RX_Valid = 1'b1;
RX_Data[6] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[7] = 1'b1; // data 7
RX_Valid = 1'b1;
RX_Data[7] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[8] = 1'b1; // data 8
RX_Valid = 1'b1;
RX_Data[8] = 1'b0; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[9] = 1'b1; // data 9
RX_Valid = 1'b1;
RX_Data[9] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[10] = 1'b1; // data 10
RX_Valid = 1'b1;
RX_Data[10] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[11] = 1'b1; // data 11
RX_Valid = 1'b1;
RX_Data[11] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[12] = 1'b1; // data 12
RX_Valid = 1'b1;
RX_Data[12] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[13] = 1'b1; // data 13
RX_Valid = 1'b1;
RX_Data[13] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[14] = 1'b1; // data 14
RX_Valid = 1'b1;
RX_Data[14] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[15] = 1'b1; // data 15
RX_Valid = 1'b1;
RX_Data[15] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
end
endmodule
Please help me out in this
Your logic uses an active-low reset. However, your testbench starts with the reset signal de-asserted (resetn=1), then asserts it (resetn=0) after 40ns. I think you need to invert the polarity in the testbench:
initial begin
clk = 1'b0;
resetn = 0; // Assert active-low reset
repeat(4) #10 clk = ~clk;
resetn = ~resetn; // De-assert reset
forever #10 clk = ~clk;
end
I have written a verilog code for scrolling hello world on seven segment display of BASYS2 board. But after compiling this code i am getting an error like this-
"ERROR:HDLCompiler:806 - "C:/Users/vishakha.ramani/Xilinx/scrollsevensegment/ssevenseg.v" Line 214: Syntax error near "endmodule"."
Kindly tell me where I am making a mistake.
enter code here
module ssevenseg(
input clock,
input reset,
output a,
output b,
output c,
output d,
output e,
output f,
output g,
output [3:0] en
);
reg [3:0] in0, in1, in2, in3; // registers to hold the LED value i.e data to be displayed
reg [28:0] tick_tock; // to count for every 1s i.e holds count of 50 M
wire click;
always #(posedge clock or posedge reset)
begin
if(reset)
tick_tock <= 0;
else if ( tick_tock==50000000)
tick_tock <= 0;
else
tick_tock <= tick_tock+1;
end
assign click = (( tick_tock==50000000)?1'b1:1'b0); // click every second
reg [3:0] count1; // to hold the count upto 9
always #(posedge click or posedge reset)
begin
if (reset)
count1 <= 0;
else
count1 <= count1 + 1;
end
always # (*)
begin
case (count1)
8'b00000000 :
begin
in0 = 4'b0001; // H
in1 = 4'b0010; // E
in2 = 4'b0011; // L
in3 = 4'b0011; // L
end
8'b00000001 :
begin
in0 = 4'b0010; // E
in1 = 4'b0011; // L
in2 = 4'b0011; // L
in3 = 4'b0100; // O
end
8'b00000010 :
begin
in0 = 4'b0011; // L
in1 = 4'b0011; // L
in2 = 4'b0100; // O
in3 = 4'b0101; // E
end
8'b00000011 :
begin
in0 = 4'b0011; // L
in1 = 4'b0100; // O
in2 = 4'b0101; // E
in3 = 4'b0100; // O
end
8'b00000100 :
begin
in0 = 4'b0100; // O
in1 = 4'b0101; // E
in2 = 4'b0100; // O
in3 = 4'b0110; // r
end
8'b00000101 :
begin
in0 = 4'b0101; // E
in1 = 4'b0100; // O
in2 = 4'b0110; // r
in3 = 4'b0011; // L
end
8'b00000110 :
begin
in0 = 4'b0100;
in1 = 4'b0110;
in2 = 4'b0011;
in3 = 4'b0111;
end
endcase
end
localparam N = 18;
reg [N-1:0]count; // the 18 bit counter that allows us to multiplex at 1000Hz
always # (posedge clock or posedge reset )
begin
if (reset)
count <= 0;
else
count <= count +1;
end
reg [3:0] display;
reg [3:0] temp_en;
always # (*)
begin
case(count[N-1:N-2])
2'b00 :
begin
display = in0;
temp_en = 4'b0111;
end
2'b01:
begin
display = in1;
temp_en = 4'b1011;
end
2'b10:
begin
display = in2;
temp_en = 4'b1101;
end
2'b11:
begin
display = in3;
temp_en = 4'b1110;
end
endcase
end
assign en = temp_en;
reg [6:0] temp_display;
always #(*)
begin
case (display)
4'b0000 : temp_display = 7'b1111110; // if we give input '0' nothing except '-' will be displayed
4'b0001 : temp_display = 7'b1001000; // This will display 'H'
4'b0010 : temp_display = 7'b0110000; // to display 'E'
4'b0011 : temp_display = 7'b1110001; // to display 'L'
4'b0100 : temp_display = 7'b0000001; // to display 'O'
4'b0101 : temp_display = 7'b1111010; // to display 'r'
4'b0110 : temp_display = 7'b1000010; // to display 'd'
default : temp_display = 7'b1111111; // blank
endcase
end
assign {a,b,c,d,e,f,g} = temp_display
endmodule
You appear to be missing a semicolon after the second-last statement:
assign {a,b,c,d,e,f,g} = temp_display
When I first tried to compile my code, I only had syntax errors and was able to fix them. Now I have errors that I cannot figure out at all. I don't know how to fix.
Here is my current code:
module p_5 (output y_out, input x_in, clk, reset_b);
parameter s_a = 2'd0;
parameter s_b = 2'd1;
parameter s_c = 2'd2;
reg Set_flag;
reg Clr_flag;
reg [1:0] state, next_state;
assign y_out = (state == s_b) || (state == s_c) ;
always # (posedge clk)
if (reset_b == 1'b0) state <= s_a;
else state <= next_state;
always # (state, x_in, flag) begin
next_state = s_a;
Set_flag = 0;
Clr_flag = 0;
case (state)
s_a: if ((x_in == 1'b1) && (flag == 1'b0))
begin next_state = s_a; Set_flag = 1; end
else if ((x_in == 1'b1) && (flag == 1'b1))
begin next_state = s_b; Set_flag = 0; end
else if (x_in == 1'b0) next_state = s_a;
s_b: if (x_in == 1'b0) next_state = s_b;
else begin next_state = s_c; Clr_flag = 1; end
s_c: if (x_in == 1'b0) next_state = s_c;
else next_state = s_a;
default: begin next_state = s_a; Clr_flag = 1'b0; Set_flag = 1'b0; end
endcase
end
always # (posedge clk)
if (reset_b == 1'b0) flag <= 0;
else if (Set_flag) flag <= 1'b1;
else if (Clr_flag) flag <= 1'b0;
endmodule
This is the test bench:
module test_5 ();
wire y_out;
reg x_in, clk, flag, reset_b;
p_5 M0 (y_out, x_in, clk, reset_b);
initial #500 $finish;
initial begin clk = 0; forever #5 clk = !clk; end
initial fork
reset_b = 1'b0;
#20 reset_b = 1;
#20 x_in = 1'b0;
#40 x_in = 1'b1;
#50 x_in = 1'b0;
#80 x_in = 1'b1;
#100 x_in = 0;
#150 x_in = 1'b1;
#160 x_in = 1'b0;
#200 x_in = 1'b1;
#230 reset_b = 1'b0;
#250 reset_b = 1'b1;
#300 x_in = 1'b0;
#300 flag = 1'b0;
join
endmodule
Errors:
p5.v:22: error: Unable to bind wire/reg/memory `flag' in `t_ques_5_50.M0'
p5.v:22: error: Unable to elaborate condition expression.
p5.v:17: error: Unable to bind wire/reg/memory `flag' in `t_ques_5_50.M0'
flag
p5.v:36: error: Could not find variable ``flag'' in ``t_ques_5_50.M0''
p5.v:37: error: Could not find variable ``flag'' in ``t_ques_5_50.M0''
p5.v:38: error: Could not find variable ``flag'' in ``t_ques_5_50.M0''
7 error(s) during elaboration.
You refer to the value flag repeatedly inside p5.v, yet it is not declared anywhere as an input, reg, or wire.
Add the appropriate declaration and it should be resolved.