ERROR: HDL COMPILER 806 - verilog

Question

I have written a verilog code for scrolling hello world on seven segment display of BASYS2 board. But after compiling this code i am getting an error like this-
"ERROR:HDLCompiler:806 - "C:/Users/vishakha.ramani/Xilinx/scrollsevensegment/ssevenseg.v" Line 214: Syntax error near "endmodule"."
Kindly tell me where I am making a mistake.
enter code here
module ssevenseg(
input clock,
input reset,
output a,
output b,
output c,
output d,
output e,
output f,
output g,
output [3:0] en
);
reg [3:0] in0, in1, in2, in3; // registers to hold the LED value i.e data to be displayed
reg [28:0] tick_tock; // to count for every 1s i.e holds count of 50 M
wire click;
always #(posedge clock or posedge reset)
begin
if(reset)
tick_tock <= 0;
else if ( tick_tock==50000000)
tick_tock <= 0;
else
tick_tock <= tick_tock+1;
end
assign click = (( tick_tock==50000000)?1'b1:1'b0); // click every second
reg [3:0] count1; // to hold the count upto 9
always #(posedge click or posedge reset)
begin
if (reset)
count1 <= 0;
else
count1 <= count1 + 1;
end
always # (*)
begin
case (count1)
8'b00000000 :
begin
in0 = 4'b0001; // H
in1 = 4'b0010; // E
in2 = 4'b0011; // L
in3 = 4'b0011; // L
end
8'b00000001 :
begin
in0 = 4'b0010; // E
in1 = 4'b0011; // L
in2 = 4'b0011; // L
in3 = 4'b0100; // O
end
8'b00000010 :
begin
in0 = 4'b0011; // L
in1 = 4'b0011; // L
in2 = 4'b0100; // O
in3 = 4'b0101; // E
end
8'b00000011 :
begin
in0 = 4'b0011; // L
in1 = 4'b0100; // O
in2 = 4'b0101; // E
in3 = 4'b0100; // O
end
8'b00000100 :
begin
in0 = 4'b0100; // O
in1 = 4'b0101; // E
in2 = 4'b0100; // O
in3 = 4'b0110; // r
end
8'b00000101 :
begin
in0 = 4'b0101; // E
in1 = 4'b0100; // O
in2 = 4'b0110; // r
in3 = 4'b0011; // L
end
8'b00000110 :
begin
in0 = 4'b0100;
in1 = 4'b0110;
in2 = 4'b0011;
in3 = 4'b0111;
end
endcase
end
localparam N = 18;
reg [N-1:0]count; // the 18 bit counter that allows us to multiplex at 1000Hz
always # (posedge clock or posedge reset )
begin
if (reset)
count <= 0;
else
count <= count +1;
end
reg [3:0] display;
reg [3:0] temp_en;
always # (*)
begin
case(count[N-1:N-2])
2'b00 :
begin
display = in0;
temp_en = 4'b0111;
end
2'b01:
begin
display = in1;
temp_en = 4'b1011;
end
2'b10:
begin
display = in2;
temp_en = 4'b1101;
end
2'b11:
begin
display = in3;
temp_en = 4'b1110;
end
endcase
end
assign en = temp_en;
reg [6:0] temp_display;
always #(*)
begin
case (display)
4'b0000 : temp_display = 7'b1111110; // if we give input '0' nothing except '-' will be displayed
4'b0001 : temp_display = 7'b1001000; // This will display 'H'
4'b0010 : temp_display = 7'b0110000; // to display 'E'
4'b0011 : temp_display = 7'b1110001; // to display 'L'
4'b0100 : temp_display = 7'b0000001; // to display 'O'
4'b0101 : temp_display = 7'b1111010; // to display 'r'
4'b0110 : temp_display = 7'b1000010; // to display 'd'
default : temp_display = 7'b1111111; // blank
endcase
end
assign {a,b,c,d,e,f,g} = temp_display
endmodule

Answer 1

You appear to be missing a semicolon after the second-last statement:
assign {a,b,c,d,e,f,g} = temp_display