Timing Issues with ZedBoard Audio Codec - audio

Question

I keep getting this error in my FPGA Design:
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
The goal of this project is to build a a system on a zedboard that has audio input/output in Vivado with an IP integrator. This is from problem 5B in "The Zynq Book Tutorials", and the instructions are summarized below.
Custom IP modules were already created, and are combined with other IP
from the source files to create a DSP system to implement on a Zynq
development board (zedboard in my case). Exercise 5A loaded the custom
IP modules into the system, and in 5B the audio codec on the ZedBoard
was loaded with some pre-packaged IP from the source files. The audio
is transferred between PL and PS through AXI-Lite connection.
The audio codec requires a second fabric clock to drive the codec, and
this is where my trouble begins. It also requires enabling the I2C
interface for communication of control signals between the PS and
codec, but I do not think this was an issue. The .xdc file was created
as a constraint for placement and route (P&R).
I am new to FPGA design, and do not understand clock functions or how to fix them. From my understanding, the problematic clock function stems from the pcore, but I am not sure what to do about this. This project was done in Vivado 2018.3. It should also be noted that all clocks in Vivado are synchronous unless specified otherwise.
Following the tutorial, I set my clock functions for the PL fabric to 100 MHz and 10 MHz. The 10 MHz clock is the driver for the codec.
The timing summary generated in an attempted P&R is:
And the problematic clock looks to be clk_fpga_0:
Here is the diagram where the highlighted block contains the clk_fpga_0 clock, and the device report is pictured below the first picture:
Here is my constraint file (XDC):
# ZedBoard LED Constraints
set_property PACKAGE_PIN T22 [get_ports {LEDs_out_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[0]}]
set_property PACKAGE_PIN T21 [get_ports {LEDs_out_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[1]}]
set_property PACKAGE_PIN U22 [get_ports {LEDs_out_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[2]}]
set_property PACKAGE_PIN U21 [get_ports {LEDs_out_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[3]}]
set_property PACKAGE_PIN V22 [get_ports {LEDs_out_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[4]}]
set_property PACKAGE_PIN W22 [get_ports {LEDs_out_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[5]}]
set_property PACKAGE_PIN U19 [get_ports {LEDs_out_0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[6]}]
set_property PACKAGE_PIN U14 [get_ports {LEDs_out_0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[7]}]
# ZedBoard Audio Codec Constraints
set_property PACKAGE_PIN AA6 [get_ports BCLK_0]
set_property IOSTANDARD LVCMOS33 [get_ports BCLK_0]
set_property PACKAGE_PIN Y6 [get_ports LRCLK_0]
set_property IOSTANDARD LVCMOS33 [get_ports LRCLK_0]
set_property PACKAGE_PIN AA7 [get_ports SDATA_I_0]
set_property IOSTANDARD LVCMOS33 [get_ports SDATA_I_0]
set_property PACKAGE_PIN Y8 [get_ports SDATA_O_0]
set_property IOSTANDARD LVCMOS33 [get_ports SDATA_O_0]
#MCLK
set_property PACKAGE_PIN AB2 [get_ports FCLK_CLK1_0]
set_property IOSTANDARD LVCMOS33 [get_ports FCLK_CLK1_0]
set_property PACKAGE_PIN AB4 [get_ports IIC_0_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_0_scl_io]
set_property PACKAGE_PIN AB5 [get_ports IIC_0_0_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_0_sda_io]
set_property PACKAGE_PIN AB1 [get_ports {GPIO_0_tri_io[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_io[0]}]
set_property PACKAGE_PIN Y5 [get_ports {GPIO_0_tri_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_io[1]}]
And my wrapper file generated from the HDL wrapper function:
--Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
--Date : Thu Dec 10 07:42:56 2020
--Host : LHAAPNTSop running 64-bit major release (build 9200)
--Command : generate_target ip_design_wrapper.bd
--Design : ip_design_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_wrapper is
port (
BCLK_0 : out STD_LOGIC;
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK1_0 : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
GPIO_0_tri_io : inout STD_LOGIC_VECTOR ( 1 downto 0 );
IIC_0_0_scl_io : inout STD_LOGIC;
IIC_0_0_sda_io : inout STD_LOGIC;
LEDs_out_0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
LRCLK_0 : out STD_LOGIC;
SDATA_I_0 : in STD_LOGIC;
SDATA_O_0 : out STD_LOGIC;
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
sws_8bits_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end ip_design_wrapper;
architecture STRUCTURE of ip_design_wrapper is
component ip_design is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
LEDs_out_0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
BCLK_0 : out STD_LOGIC;
LRCLK_0 : out STD_LOGIC;
SDATA_O_0 : out STD_LOGIC;
FCLK_CLK1_0 : out STD_LOGIC;
IIC_0_0_sda_i : in STD_LOGIC;
IIC_0_0_sda_o : out STD_LOGIC;
IIC_0_0_sda_t : out STD_LOGIC;
IIC_0_0_scl_i : in STD_LOGIC;
IIC_0_0_scl_o : out STD_LOGIC;
IIC_0_0_scl_t : out STD_LOGIC;
GPIO_0_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_0_tri_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
sws_8bits_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
SDATA_I_0 : in STD_LOGIC
);
end component ip_design;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal GPIO_0_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal GPIO_0_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal GPIO_0_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal GPIO_0_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal GPIO_0_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal GPIO_0_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal GPIO_0_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal GPIO_0_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal IIC_0_0_scl_i : STD_LOGIC;
signal IIC_0_0_scl_o : STD_LOGIC;
signal IIC_0_0_scl_t : STD_LOGIC;
signal IIC_0_0_sda_i : STD_LOGIC;
signal IIC_0_0_sda_o : STD_LOGIC;
signal IIC_0_0_sda_t : STD_LOGIC;
begin
GPIO_0_tri_iobuf_0: component IOBUF
port map (
I => GPIO_0_tri_o_0(0),
IO => GPIO_0_tri_io(0),
O => GPIO_0_tri_i_0(0),
T => GPIO_0_tri_t_0(0)
);
GPIO_0_tri_iobuf_1: component IOBUF
port map (
I => GPIO_0_tri_o_1(1),
IO => GPIO_0_tri_io(1),
O => GPIO_0_tri_i_1(1),
T => GPIO_0_tri_t_1(1)
);
IIC_0_0_scl_iobuf: component IOBUF
port map (
I => IIC_0_0_scl_o,
IO => IIC_0_0_scl_io,
O => IIC_0_0_scl_i,
T => IIC_0_0_scl_t
);
IIC_0_0_sda_iobuf: component IOBUF
port map (
I => IIC_0_0_sda_o,
IO => IIC_0_0_sda_io,
O => IIC_0_0_sda_i,
T => IIC_0_0_sda_t
);
ip_design_i: component ip_design
port map (
BCLK_0 => BCLK_0,
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FCLK_CLK1_0 => FCLK_CLK1_0,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
GPIO_0_tri_i(1) => GPIO_0_tri_i_1(1),
GPIO_0_tri_i(0) => GPIO_0_tri_i_0(0),
GPIO_0_tri_o(1) => GPIO_0_tri_o_1(1),
GPIO_0_tri_o(0) => GPIO_0_tri_o_0(0),
GPIO_0_tri_t(1) => GPIO_0_tri_t_1(1),
GPIO_0_tri_t(0) => GPIO_0_tri_t_0(0),
IIC_0_0_scl_i => IIC_0_0_scl_i,
IIC_0_0_scl_o => IIC_0_0_scl_o,
IIC_0_0_scl_t => IIC_0_0_scl_t,
IIC_0_0_sda_i => IIC_0_0_sda_i,
IIC_0_0_sda_o => IIC_0_0_sda_o,
IIC_0_0_sda_t => IIC_0_0_sda_t,
LEDs_out_0(7 downto 0) => LEDs_out_0(7 downto 0),
LRCLK_0 => LRCLK_0,
SDATA_I_0 => SDATA_I_0,
SDATA_O_0 => SDATA_O_0,
btns_5bits_tri_i(4 downto 0) => btns_5bits_tri_i(4 downto 0),
sws_8bits_tri_i(7 downto 0) => sws_8bits_tri_i(7 downto 0)
);
end STRUCTURE;