This code is used to turn a led on if a switch is on.
This the top module.
module myb(
input clk,
input execute,
input switch,
output reg k
);
logic [5:0] led;
always#(posedge clk)
begin
if(switch)
led[0] = 1;
end
endmodule
This is the constraint
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports k]
set_property IOSTANDARD LVCMOS33 [get_ports k]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN T18 [get_ports execute]
set_property IOSTANDARD LVCMOS33 [get_ports execute]
#------------------------------------------------------------
#---------------------- Clock signal ------------------------
#------------------------------------------------------------
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [ get_ports clk]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
set_property PACKAGE_PIN V17 [get_ports {switch]
set_property IOSTANDARD LVCMOS33 [get_ports {switch]
But somehow, nothing changes. I also tried it with buttons,debouncers etc. What am I doing wrong?
As Serge said: for a signal to come out of an FPGA your top module should have an output port. Did your tool gave you no warning or errors? Because your constraints could not be fulfilled!
Secondly I would generate two outputs: one high and one low. This guarantees that at least one of the LEDs will light up.
Make sure to thorough check the ports to FPGA pins mapping. It is, apart from coding errors, the most common source of errors when I/O pins don't work.
You where very good with getting back to basic code to test your I/O. That is the right way of debugging. You could have gone one more step and omitted the clock as well. Just: assign led = 6'b101010; Then after you get them to work add the clock.
Final remark: your output k is unused and undefined.
Related
I keep getting this error in my FPGA Design:
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
The goal of this project is to build a a system on a zedboard that has audio input/output in Vivado with an IP integrator. This is from problem 5B in "The Zynq Book Tutorials", and the instructions are summarized below.
Custom IP modules were already created, and are combined with other IP
from the source files to create a DSP system to implement on a Zynq
development board (zedboard in my case). Exercise 5A loaded the custom
IP modules into the system, and in 5B the audio codec on the ZedBoard
was loaded with some pre-packaged IP from the source files. The audio
is transferred between PL and PS through AXI-Lite connection.
The audio codec requires a second fabric clock to drive the codec, and
this is where my trouble begins. It also requires enabling the I2C
interface for communication of control signals between the PS and
codec, but I do not think this was an issue. The .xdc file was created
as a constraint for placement and route (P&R).
I am new to FPGA design, and do not understand clock functions or how to fix them. From my understanding, the problematic clock function stems from the pcore, but I am not sure what to do about this. This project was done in Vivado 2018.3. It should also be noted that all clocks in Vivado are synchronous unless specified otherwise.
Following the tutorial, I set my clock functions for the PL fabric to 100 MHz and 10 MHz. The 10 MHz clock is the driver for the codec.
The timing summary generated in an attempted P&R is:
And the problematic clock looks to be clk_fpga_0:
Here is the diagram where the highlighted block contains the clk_fpga_0 clock, and the device report is pictured below the first picture:
Here is my constraint file (XDC):
# ZedBoard LED Constraints
set_property PACKAGE_PIN T22 [get_ports {LEDs_out_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[0]}]
set_property PACKAGE_PIN T21 [get_ports {LEDs_out_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[1]}]
set_property PACKAGE_PIN U22 [get_ports {LEDs_out_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[2]}]
set_property PACKAGE_PIN U21 [get_ports {LEDs_out_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[3]}]
set_property PACKAGE_PIN V22 [get_ports {LEDs_out_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[4]}]
set_property PACKAGE_PIN W22 [get_ports {LEDs_out_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[5]}]
set_property PACKAGE_PIN U19 [get_ports {LEDs_out_0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[6]}]
set_property PACKAGE_PIN U14 [get_ports {LEDs_out_0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs_out_0[7]}]
# ZedBoard Audio Codec Constraints
set_property PACKAGE_PIN AA6 [get_ports BCLK_0]
set_property IOSTANDARD LVCMOS33 [get_ports BCLK_0]
set_property PACKAGE_PIN Y6 [get_ports LRCLK_0]
set_property IOSTANDARD LVCMOS33 [get_ports LRCLK_0]
set_property PACKAGE_PIN AA7 [get_ports SDATA_I_0]
set_property IOSTANDARD LVCMOS33 [get_ports SDATA_I_0]
set_property PACKAGE_PIN Y8 [get_ports SDATA_O_0]
set_property IOSTANDARD LVCMOS33 [get_ports SDATA_O_0]
#MCLK
set_property PACKAGE_PIN AB2 [get_ports FCLK_CLK1_0]
set_property IOSTANDARD LVCMOS33 [get_ports FCLK_CLK1_0]
set_property PACKAGE_PIN AB4 [get_ports IIC_0_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_0_scl_io]
set_property PACKAGE_PIN AB5 [get_ports IIC_0_0_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_0_sda_io]
set_property PACKAGE_PIN AB1 [get_ports {GPIO_0_tri_io[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_io[0]}]
set_property PACKAGE_PIN Y5 [get_ports {GPIO_0_tri_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_io[1]}]
And my wrapper file generated from the HDL wrapper function:
--Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
--Date : Thu Dec 10 07:42:56 2020
--Host : LHAAPNTSop running 64-bit major release (build 9200)
--Command : generate_target ip_design_wrapper.bd
--Design : ip_design_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_wrapper is
port (
BCLK_0 : out STD_LOGIC;
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK1_0 : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
GPIO_0_tri_io : inout STD_LOGIC_VECTOR ( 1 downto 0 );
IIC_0_0_scl_io : inout STD_LOGIC;
IIC_0_0_sda_io : inout STD_LOGIC;
LEDs_out_0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
LRCLK_0 : out STD_LOGIC;
SDATA_I_0 : in STD_LOGIC;
SDATA_O_0 : out STD_LOGIC;
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
sws_8bits_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end ip_design_wrapper;
architecture STRUCTURE of ip_design_wrapper is
component ip_design is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
LEDs_out_0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
BCLK_0 : out STD_LOGIC;
LRCLK_0 : out STD_LOGIC;
SDATA_O_0 : out STD_LOGIC;
FCLK_CLK1_0 : out STD_LOGIC;
IIC_0_0_sda_i : in STD_LOGIC;
IIC_0_0_sda_o : out STD_LOGIC;
IIC_0_0_sda_t : out STD_LOGIC;
IIC_0_0_scl_i : in STD_LOGIC;
IIC_0_0_scl_o : out STD_LOGIC;
IIC_0_0_scl_t : out STD_LOGIC;
GPIO_0_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_0_tri_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
sws_8bits_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
SDATA_I_0 : in STD_LOGIC
);
end component ip_design;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal GPIO_0_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal GPIO_0_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal GPIO_0_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal GPIO_0_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal GPIO_0_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal GPIO_0_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal GPIO_0_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal GPIO_0_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal IIC_0_0_scl_i : STD_LOGIC;
signal IIC_0_0_scl_o : STD_LOGIC;
signal IIC_0_0_scl_t : STD_LOGIC;
signal IIC_0_0_sda_i : STD_LOGIC;
signal IIC_0_0_sda_o : STD_LOGIC;
signal IIC_0_0_sda_t : STD_LOGIC;
begin
GPIO_0_tri_iobuf_0: component IOBUF
port map (
I => GPIO_0_tri_o_0(0),
IO => GPIO_0_tri_io(0),
O => GPIO_0_tri_i_0(0),
T => GPIO_0_tri_t_0(0)
);
GPIO_0_tri_iobuf_1: component IOBUF
port map (
I => GPIO_0_tri_o_1(1),
IO => GPIO_0_tri_io(1),
O => GPIO_0_tri_i_1(1),
T => GPIO_0_tri_t_1(1)
);
IIC_0_0_scl_iobuf: component IOBUF
port map (
I => IIC_0_0_scl_o,
IO => IIC_0_0_scl_io,
O => IIC_0_0_scl_i,
T => IIC_0_0_scl_t
);
IIC_0_0_sda_iobuf: component IOBUF
port map (
I => IIC_0_0_sda_o,
IO => IIC_0_0_sda_io,
O => IIC_0_0_sda_i,
T => IIC_0_0_sda_t
);
ip_design_i: component ip_design
port map (
BCLK_0 => BCLK_0,
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FCLK_CLK1_0 => FCLK_CLK1_0,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
GPIO_0_tri_i(1) => GPIO_0_tri_i_1(1),
GPIO_0_tri_i(0) => GPIO_0_tri_i_0(0),
GPIO_0_tri_o(1) => GPIO_0_tri_o_1(1),
GPIO_0_tri_o(0) => GPIO_0_tri_o_0(0),
GPIO_0_tri_t(1) => GPIO_0_tri_t_1(1),
GPIO_0_tri_t(0) => GPIO_0_tri_t_0(0),
IIC_0_0_scl_i => IIC_0_0_scl_i,
IIC_0_0_scl_o => IIC_0_0_scl_o,
IIC_0_0_scl_t => IIC_0_0_scl_t,
IIC_0_0_sda_i => IIC_0_0_sda_i,
IIC_0_0_sda_o => IIC_0_0_sda_o,
IIC_0_0_sda_t => IIC_0_0_sda_t,
LEDs_out_0(7 downto 0) => LEDs_out_0(7 downto 0),
LRCLK_0 => LRCLK_0,
SDATA_I_0 => SDATA_I_0,
SDATA_O_0 => SDATA_O_0,
btns_5bits_tri_i(4 downto 0) => btns_5bits_tri_i(4 downto 0),
sws_8bits_tri_i(7 downto 0) => sws_8bits_tri_i(7 downto 0)
);
end STRUCTURE;
I am a FPGA beginner and recently I tried a very simple flowing-light program that went well on my computer. However, the LEDs on my Zybo remain the initial state(only the leftmost LED lights up) no matter how long I wait. I searched for the solution for a week and tried any way I can think of even borrowed another board from my friend, yet the problem just exists.
Here's my verilog code
top.v
module top(
input clk,
output [3:0] led
);
reg [23:0] cnt_reg;
reg [3:0] led_reg;
initial begin
cnt_reg <= 0;
led_reg <= 4'b1000;
end
always #(posedge clk)begin
if(cnt_reg == 24'h00000f)
begin
if(led_reg == 4'b0001)
led_reg <= 4'b1000;
else
led_reg <= led_reg>>1;
end
else
cnt_reg <= cnt_reg + 1;
end
assign led = led_reg;
endmodule
Here's my constraint
set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1
set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk
Here's my testbench
`timescale 1ns/1ps
module tb();
reg clk;
wire [3:0] led;
top U0 (.clk(clk), .led(led));
parameter Period = 10;
always begin
clk = 1'b0;
#(Period/2) clk=1'b1;
#(Period/2);
end
initial begin
clk = 1'b0;
#1000000;
end
endmodule
And the simulation result shows below:
the simulation result
After programming my device
LEDs just remain the initial state
After programming my device LEDs just remain the initial state
Your LEDS do not remain in the init state because all four of them light up. In the init state you have "1000". Which would be one on and three off (or vice versa depending on on how they are connected).
What is happening is that you board behave just like your simulation result shows you: every clock cycle the next LED lights up. Your clock is probably around 10MHz or 100MHz so you don't see that.
To fix this you need two things:
You need to count longer. How big depends on your clock frequency so find out what it is.
Fix your counter code. Once the counter value is reached it no longer counts. It stays at 24'h00000F. You waveform does not show that but your code is obvious.
I am fairly new to Verilog and FPGA development. I am currently working on a project to control two motors using a Basys 3 board and an H bridge.
The module is currently built to use PWM to control the motor speed, sending the output to the ena and enb pins on the H-Bridge. The H inputs are currently constant for the sake of testing the PWM control.
Well long story short I have run into a variety of I/O errors that I just haven't been able to fully wrap my head around.
Here is my primary module:
module RDrive(
input clock,
input BUTTON,
input H1, H2, H3, H4,
output ena, enb
);
wire clock, BUTTON, H1, H2, H3, H4;
reg[1:0] speed;
reg[3:0] counter, width;
reg PWMtemp;
wire ena, enb;
// initial values
initial begin
counter <= 4'b0000;
speed = 0;
PWMtemp <= 0;
width <= 0;
end
// Every button press increments speed value
always # (posedge BUTTON)
begin
speed <= speed + 1;
// width adjusted for PWM module
case (speed)
2'b00 : width <= 4'b0000;
2'b01 : width <= 4'b0101;
2'b10 : width <= 4'b1010;
2'b11 : width <= 4'b1111;
default : width <= 4'b0000;
endcase
end
// PWM
always # (posedge clock)
begin
if (counter < width) PWMtemp <= 1;
else PWMtemp <= 0;
counter <= counter + 1;
end
assign ena = PWMtemp;
assign enb = PWMtemp;
endmodule
Here is my test bench:
module RDrive_TB(
);
reg clock;
wire ena = 0;
wire enb = 0;
reg BUTTON, H1, H2, H3, H4;
initial begin
BUTTON = 0;
clock = 0;
// H values for testing PWM speed control
H1 = 1;
H2 = 0;
H3 = 1;
H4 = 0;
// Simulating button presses
#1000;
BUTTON = 1;
#10;
BUTTON = 0;
#1000;
BUTTON = 1;
#10;
BUTTON = 0;
#1000;
BUTTON = 1;
#10;
BUTTON = 0;
#1000;
BUTTON = 1;
#10;
BUTTON = 0;
end
// clock generator
always begin
#1 clock = ~clock;
end
RDrive RDriveTest(clock, BUTTON, H1, H2, H3, H4, ena, enb);
endmodule
and here are my constraints:
set_property PACKAGE_PIN W5 [get_ports CLK100MH]
set_property IOSTANDARD LVCMOS33 [get_ports CLK100MH]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports
CLK100MH]
set_property PACKAGE_PIN U18 [get_ports BUTTON]
set_property IOSTANDARD LVCMOS33 [get_ports BUTTON]
##Sch name = JA8
set_property PACKAGE_PIN K2 [get_ports {enb}]
set_property IOSTANDARD LVCMOS33 [get_ports {enb}]
The first error (occurred during implementation) that I got was this:
ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG.
I did some research, and I think the problem was a result of
always # (posedge BUTTON)
not being exactly in time with the clock.
So I added this line to the constraints to ignore the error:
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets BUTTON_IBUF]
This allowed me to run the implementation successfully. However, I encountered the following error when attempting to generate the bitstream:
ERROR: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 4 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value.
From what I understand, this error occurs when inputs/outputs are not assigned an initial value, so they assume whatever the 'DEFAULT' value is. I fiddled around with the initial values and value types of each of the "problem pins" that were listed. I was able to fix most of them, but currently 'clock' is the only remaining problem pin. I've been trying to fix clock for a while now with no luck.
Some help would be greatly appreciated, thanks!
1/ You should not use # (posedge BUTTON) for two reasons:
You have not de-bounced the button so a single push can trigger multiple speed increments.
In simple design like that everything should run of a single clock.
You should synchronize your button input to the clock and then add a counter + logic to check if the signal is stable (bouncing has stopped).
2/ The error message is very clear and specific:
Unspecified I/O Standard: 1 out of 4 logical ports....
All I did was check all your I/O ports and check your pin constraints. I see no constraint for the ena signal.
I wanted to make a 4-bit counter on Basys3 board using Vivado. I wrote a code for it in verilog. I am not able to generate the bit stream. I have pasted stopwatch.v module and constraint file. The onboard clock speed of Basys3 is 100MHz.
//`timescale 1ns/1ps
module stopwatch( input clk, input reset, input start, input pause, output reg [3:0] out);
reg [26:0] clock;
reg starter;
always #(posedge clk or posedge reset)
begin
if (reset)
begin
out <= 0;
clock <= 0;
end
else if (starter)
begin
if (clock == 25'd10000000)
begin
out <= out + 1'b1;
clock <= 0;
end
else
clock <= clock + 1'b1;
end
end // always # (posedge clk or posedge reset)
always #(*)
begin
if (start)
starter <= 1'b1;
else if (pause)
starter <= 0;
end
endmodule // stopwatch
Constraint_file.xdc
set_property PACKAGE_PIN U18 [get_ports {reset}]
set_property PACKAGE_PIN T18 [get_ports {start}]
set_property PACKAGE_PIN U17 [get_ports {pause}]
set_property PACKAGE_PIN U16 [get_ports {out[0]}]
set_property PACKAGE_PIN E19 [get_ports {out[1]}]
set_property PACKAGE_PIN U19 [get_ports {out[2]}]
set_property PACKAGE_PIN V19 [get_ports {out[3]}]
set_property PACKAGE_PIN W5 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports {reset start pause out}]
Below is the error I am keep getting:
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pause_IBUF] >
pause_IBUF_inst (IBUF.O) is locked to IOB_X0Y14
and pause_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
The tools is complaining about your choice for the 'pause' I/O buffer.
It says you should use a global clock buffer input (BUFG) for that signal.
It has routed the signal through a global clock buffer "BUFGCTRL_X0Y0".
This might have to do with the fact that 'starter' is a latch and Vivado thinks your pause signal is a clock. This piece of code is wrong:
always #(*)
begin
if (start)
starter <= 1'b1;
else if (pause)
starter <= 0;
end
First of all: In an always combinatorial block you do not use non-blocking assignments. You use '='
Secondly : there is no closing 'else' so you get a latch.
Or was this the code you wanted:
assign starter = start & ~pause;
Alternative you could move that code, as it is, into your clocked section.
In that case make sure you reset "starter" as well.
I have written two codes for implementation of DAC in Spartan 3E starter Kit, they seem to be working perfectly in simulation but when i attach them to chipscope and load on board I always get a zero value. I have also noticed that there were no critical warnings.
Code 1:
module dac_state_d(
input dacclk,
input reset,
input [31:0] dacdata,
output reg[31:0] previousdata,
output reg dac_mosi,
output reg dac_miso,
output reg dac_cs,
output reg dac_sck,
output reg dac_clr,
output reg spi_ss_b,
output reg sf_ce0,
output reg fpga_init_b,
output reg amp_cs,
output reg ad_conv,
output reg [2:0] state,
output reg ack
);
integer index=0;
parameter idle=3'b000, ready=3'b001, delay=3'b010, trans=3'b011, read=3'b100, increment=3'b101, check=3'b110;
initial begin//setting different registers on spi bus and initialization
spi_ss_b='b1;
amp_cs='b1;
ad_conv='b0;
sf_ce0='b1;
fpga_init_b='b0;
end
always #(posedge dacclk or posedge reset) begin
if (reset) begin
index<=0;
dac_mosi<=0;
dac_clr<=0;
dac_sck<=0;
dac_cs<=1;
end
else begin
dac_clr<=1;
case(state)
idle: begin
dac_sck <= 0;
dac_cs <= 1;
index <= 0;
dac_mosi <= 0;
ack <= 1;
state <= ready;
end
ready: begin
ack <= 0;
dac_cs <= 0;
dac_sck <= 0;
dac_mosi <= dacdata[31-index];
state <= delay;
end
delay: begin
state <= trans;
end
trans: begin
dac_sck <= 1;
state <= read;
end
read: begin
dac_sck <= 1;
previousdata[31-index]<=dac_miso;
state <= increment;
end
increment: begin
dac_sck <= 1;
index <= index + 1;
state <= check;
end
check: begin
dac_sck <= 1;
if (31-index < 0) begin
state <= idle; end
else begin
state <= ready;
end
end
endcase
end
end
endmodule
with its top module defined as
reg [31:0] dacdata;
wire [31:0] previousdata;
reg [3:0] command, address;
wire dac_miso_w;
assign dac_miso_w=dac_miso;
wire dacclk;
DACCLK clock(.clk(clk),
.dacclk(dacclk)
);
dac_state_d daq_run(.dacclk(dacclk),
.reset(reset),
.dacdata(dacdata),
.previousdata(previousdata),
.dac_mosi(dac_mosi),
.dac_miso(dac_miso_w),
.dac_clr(dac_clr),
.dac_cs(dac_cs),
.spi_ss_b(spi_ss_b),
.sf_ce0(sf_ce0),
.fpga_init_b(fpga_init_b),
.amp_cs(amp_cs),
.ad_conv(ad_conv),
.dac_sck(dac_sck),
.state(state),
.ack(ack)
);
initial begin
command<=4'b0011;
address<=4'b1111;
end
always # (posedge clk) begin
if (ack) begin
dacdata[31:24]<=8'b00000000;
dacdata[23:20]<=command;
dacdata[19:16]<=address;
dacdata[15:4]<=data;
dacdata[3:0]<=4'b0000;
pre_data<=previousdata[15:4];
end
else begin dacdata<=0; end
end
//chipscope-------------------
wire[11:0] D;
wire R;
wire[35:0] CONTROL;
assign D=data;
assign R=reset;
ICON cs_con(.CONTROL0(CONTROL)); //INOUT BUS [35:0]
VIO cs_vio (.CONTROL(CONTROL), // INOUT BUS [35:0]
.ASYNC_IN({pre_data,state,ack}), // IN BUS [12:0]
.ASYNC_OUT({D,R}) // OUT BUS [12:0]
);
//----------------------------------------------------------------------------
endmodule
obviously top module has also I/O port description.
Code 2:
wire dacclk;
DACCLK clock(.clk(clk),
.dacclk(dacclk)
);
initial begin//setting different registers on spi bus and initialization
spi_ss_b='b1;
amp_cs='b1;
ad_conv='b0;
fpga_init_b='b0;
dac_clr=1;
dac_cs=1;
dacstate<=0;
//StrataFLASH must be disabled to prevent it driving the SDI line with its D0 output
//or conflicting with the LCD display
strataflash_oe <= 1;
strataflash_ce <= 1;
strataflash_we <= 1;
end
always#(posedge dacclk) begin
case (dacstate)
//------------------------------Bit 31 to 24 Don't Care----------------------------------
0: begin//idle and allotment cycle(31-->x)
ack=0;
dac_cs=0;
dac_sck=0;
dacstate=1;
end
1: begin//read write cycle (31)
dac_sck=1;
dacstate=2;
end
2: begin//idle and allotment cycle(30-->x)
dacstate=3;
dac_sck=0;
end
3: begin//read write cycle(30)
dac_sck=1;
dacstate=4;
.....
62: begin//idle and allotment cycle(0-->x)
dac_sck=0;
dacstate=63;
end
63: begin//read write cycle(0)
dac_sck=1;
dacstate=64;
end
64: begin//Acknowledging completion of data transfer to DAC
dac_cs=1;
ack=1;
dacstate=65;
end
65: begin if (reset) begin dacstate=0; end
else begin dacstate=65; end end//idle or reset
default: begin dacstate=0; end
endcase
end
endmodule
UCF file i used is as follows
NET "clk" PERIOD = 20.0ns HIGH 50%;
NET "clk" LOC = "C9" | IOSTANDARD = LVTTL;
NET"dac_miso" LOC= "N10" | IOSTANDARD= LVCMOS33 ;
NET"dac_mosi" LOC= "T4" | IOSTANDARD= LVCMOS33 | SLEW= SLOW | DRIVE= 8 ;
NET"dac_sck" LOC= "U16" | IOSTANDARD= LVCMOS33 | SLEW= SLOW | DRIVE= 8 ;
NET"dac_cs" LOC= "N8" | IOSTANDARD= LVCMOS33 | SLEW= SLOW | DRIVE= 8 ;
NET"dac_clr" LOC= "P8" | IOSTANDARD= LVCMOS33 | SLEW= SLOW | DRIVE= 8 ;
NET "fpga_init_b" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
NET "ad_conv" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "amp_cs" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW |DRIVE = 6 ;
NET "spi_ss_b" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "sf_ce0" LOC = "D16" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
NET "reset" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN;
I don't expect some-one to solve my problem but I feel helpless as i am debugging these codes from past 2 weeks and i am unable to find any problem. It will be really helpful if someone can point me towards error. I also went through some sample codes but as all are written in VHDL hence they were not great help to me. still i tried to match the logic and found it to be the same.
The error in code is very basic, actually in connection to VIO. Inputs can't be connected to VIO as VIO is internal hence need to connect the wire only. Also, there is assignment of input to wire and Wire is reassigned by VIO, which is not acceptable.