I am trying to write a 100-ripple carry adder. Fist I design a full adder. Then I need to connect 100 full adders.
I am getting errors:
Error (10170): Verilog HDL syntax error at top_module.v(11) near text:
"instance1"; expecting "<=", or "=", or "+=", or "-=", or "*=", or
"/=", or "%=", or "&=", or "|=", or "^=", or "<<=", or ">>=", or
"<<<=", or ">>>=", or "++", or "--". Check for and fix any syntax
errors that appear immediately before or at the specified keyword. The
Intel FPGA Knowledge Database contains many articles with specific
details on how to resolve this error. Visit the Knowledge Database at
https://www.altera.com/support/support-resources/knowledge-base/search.html
and search for this specific error message number. File:
/var/www/verilog/work/vlg7ccmQf_dir/top_module.v Line: 11
module top_module(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );
assign {cout[0],sum[0]}=a[0]+b[0]+cin;
always# (*)
begin
for (int i=1; i<$bits(a);i++)
full_adder instance1(
.a_1(a[i]),
.b_1(b[i]),
.cin_1(cout[i-1]),
.cout_1(cout[i]),
.sum_1(sum[i])
);
end
endmodule
module full_adder(
input a_1, b_1,
input cin_1,
output cout_1,
output sum_1
);
assign {cout_1,sum_1}=cin_1+a_1+b_1;
endmodule
well, you cannot instantiate a module inside of an always block. Try a generate block instead:
...
assign {cout[0],sum[0]}=a[0]+b[0]+cin;
genvar i;
for ( i=1; i<$bits(a);i=i+1)
full_adder instance1(
.a_1(a[i]),
.b_1(b[i]),
.cin_1(cout[i-1]),
.cout_1(cout[i]),
.sum_1(sum[i])
);
...
You cannot instantiate a module inside of a procedural block. Try to use generate block instead:
The final code should be like this:
module top_module(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum
);
assign {cout[0],sum[0]}=a[0]+b[0]+cin;
genvar i;
generate
for ( i = 1; i < $size(a); i++ ) begin : gen
full_adder instance1(
.a_1(a[i]),
.b_1(b[i]),
.cin_1(cout[i-1]),
.cout_1(cout[i]),
.sum_1(sum[i])
);
end : gen
endgenerate
endmodule
module full_adder(
input a_1, b_1,
input cin_1,
output cout_1,
output sum_1
);
assign {cout_1,sum_1}=cin_1+a_1+b_1;
endmodule
Please pay attention to the for-label ":gen", it is necessary and the code will not work without it.
Related
I'm writing in SystemVerilog, and I'm attempting to make a n-bit look-ahead adder. I have issues with generate; I get the following errors:
** Error: design.sv(13): Module 'fulladder' is not defined.
# For instance 'f0' at path 'carry_lookahead_adder_tb.carry_lookahead_inst'
# ** Error: design.sv(17): Module 'fulladder' is not defined.
# For instance 'fi' at path 'carry_lookahead_adder_tb.carry_lookahead_inst.f_loop'
# ** Error: design.sv(17): Module 'fulladder' is not defined.
# For instance 'fi' at path 'carry_lookahead_adder_tb.carry_lookahead_inst.f_loop'
# Optimization failed
Line 13 is fulladder f0...
module carry_lookahead_adder
#(parameter WIDTH=32)
(input logic [WIDTH-1:0] i_add1,
input logic [WIDTH-1:0] i_add2,
output logic [WIDTH:0] o_result
);
logic [WIDTH:0] w_C;
logic [WIDTH-1:0] w_G, w_P, w_SUM;
//Generate full adders
genvar i;
fulladder f0 (i_bit1(i_add1[0]), i_bit2(i_add2[0]),i_carry(w_C[0]), o_sum(w_SUM[0]), o_carry());
generate for (i= 1; i<WIDTH; i++)
begin : f_loop
fulladder fi
(i_bit1(i_add1[i]),
i_bit2(i_add2[i]),
i_carry(w_C[i]),
o_sum(w_SUM[i]),
o_carry()
);
end
endgenerate
genvar jj;
generate
for (jj=0; jj<WIDTH; jj++)
begin
assign w_G[jj] = i_add1[jj] & i_add2[jj];
assign w_P[jj] = i_add1[jj] | i_add2[jj];
assign w_C[jj+1] = w_G[jj] | (w_P[jj] & w_C[jj]);
end
endgenerate
assign w_C[0] = 1'b0; //No carry input
assign o_result = {w_C[WIDTH], w_SUM};
endmodule
I know I'm creating/calling the function wrong, but I can't find any good resources on how to do it right.
These errors have nothing to do with the generate construct. The errors are simply telling you that the fulladder module is not defined. This means that you did not include the module when you compiled your Verilog code.
Note that the 1st error message refers to instance f0 which is not inside the generate. I get the same error message when I run your code on edaplayground with all of the generate code removed:
module carry_lookahead_adder
#(parameter WIDTH=32)
(input logic [WIDTH-1:0] i_add1,
input logic [WIDTH-1:0] i_add2,
output logic [WIDTH:0] o_result
);
logic [WIDTH:0] w_C;
logic [WIDTH-1:0] w_G, w_P, w_SUM;
//Generate full adders
genvar i;
fulladder f0 (i_bit1(i_add1[0]), i_bit2(i_add2[0]),i_carry(w_C[0]), o_sum(w_SUM[0]), o_carry());
endmodule
# ** Error: testbench.sv(13): Module 'fulladder' is not defined.
# For instance 'f0' at path 'carry_lookahead_adder'
The design.sv file does not appear to have the fulladder module. You either need to add the module to that file, or (more likely) instruct your simulator to compile the file with the fulladder module in it.
You also have syntax errors in your module instantiations. When you use connections by name, you need to use a period before the port name. For example, you need to use .i_bit1(i_add1[0]), etc.:
fulladder f0 (.i_bit1(i_add1[0]), .i_bit2(i_add2[0]),.i_carry(w_C[0]), .o_sum(w_SUM[0]), .o_carry());
I am trying to implement a 4 bit right shifter using gate level but i got unknown result for some reason, my mux work ok but when i try testbench for my shifter it give back something like this:
a=0010 b=01 c=0000
a=1111 b=01 c=00xx
Please help!!!! Thank you very much
module mux2(a,b,sel,c);
output c;
input a,b,sel;
wire net0,net1,net2;
not m1(net0,sel);
and m2(net1,a,net0);
and m3(net2,b,sel);
or m4(c,net1,net2);
endmodule
module mux4(a,sel,c);
output c;
input [1:0]sel;
input[3:0]a;
wire mux_1,mux_2;
mux2 m1(a[3],a[2],sel[0],mux_1);
mux2 m2(a[1],a[0],sel[0],mux_2);
mux2 m3(mux_1,mux_2,sel[1],c);
endmodule
module shift4bitright(c,a,b);
output [3:0]c;
input [3:0]a;
input [1:0]b;
wire [3:0]d=4'h0,d1=4'h0,d2=4'h0,d3=4'h0;
assign d[0]=a[3];
assign d1[0]=a[2]; assign d1[1]=a[3];
assign d2[0]=a[1]; assign d2[1]=a[2]; assign d2[2]=a[3];
assign d3[0]=a[0]; assign d3[1]=a[1];assign d3[2]=a[2];assign d3[3]=a[3];
mux4 m1(d,b,c[3]);
mux4 m2(d1,b,c[2]);
mux4 m3(d2,b,c[1]);
mux4 m4(d3,b,c[0]);
endmodule
`timescale 10ns/1ns
module shift4bitright_tb;
wire [3:0]c;
reg [3:0]a;
reg [1:0]b;
shift4bitright s1(.c(c),.a(a),.b(b));
initial begin
$monitor("a=%b b=%b c=%b",a,b,c);
a=4'h2;
b=2'd1;
#50
a=4'hf;
b=2'd1;
end
endmodule
This statement declared a wire type signal d as well as its driver cone (NOT initial value), which is a constant 0 in this case:
wire [3:0]d=4'h0;
Just below it, there's another a[3] driving d[0]:
assign d[0]=a[3];
This creates a multi-driven logic, hence x occurs.
To solve it, change it similar to:
wire [3:0] d;
assign d = {3'h0, a[3]};
I am trying to make a simple 32 bit ALU with an overflow flag, and then output the inputs and results of the ALU to the screen, but I encountered some problems with connecting the elements for the test bench. I got this error:
test_32bALU.v:15: error: Wrong number of ports. Expecting 4, got 5.
test_32bALU.v:33: error: Unable to bind wire/reg/memory
test_unit.overflow' inalu_test'
2 error(s) during elaboration.
I am just starting with Verilog and I have a basic idea of the syntax. I know I am not supposed to ask debugging questions, but this is my only hope. My professor or TA wouldn't respond to me requests for help. I would appreciate it if anyone here could help me point out my mistakes.
This is my 32bALU.v file:
module alu(
input signed[31:0] a,b,
input[3:0] opcode;
output signed[31:0] c;
output overflow;
);
reg signed[31:0] result;
assign c = result;
reg tmp;
parameter
add = 4'b0000,
sub = 4'b0110,
sla = 4'b0001,
srai = 4'b0011;
always #(a,b,opcode)
begin
case(opcode)
add:
begin
c = a + b;
end
endcase
end
always #(c)
begin
if (c[32:31] == (2'b11 | 2'b10)) // Overflow
begin
tmp = 1'b1;
assign overflow = tmp;
end
else begin
tmp = 1'b0;
assign overflow = tmp;
end
end
assign result = c[31:0];
endmodule
test_32bALU.v
`timescale 1ns/1ps
module alu_test;
// Inputs
reg[31:0] a,b;
reg[2:0] opcode;
// Outputs
wire[31:0] c;
//wire [1:0] zero;
wire [1:0] overflow;
//wire [1:0] neg;
alu test_unit(
a,b, // Inputs
opcode,
c,
overflow
);
parameter
add = 4'b0000,
sub = 4'b0110,
sla = 4'b0001,
srai = 4'b0011;
initial begin
$display("op: a : b : c : reg_A : reg_B : reg_C");
$monitor(" %h:%h:%h:%h:%h:%h:%h",
opcode, a, b, c, test_unit.a, test_unit.b, test_unit.c);
$monitor("%h", test_unit.overflow);
//// add
#10 a=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#10 b=32'b0000_0000_0000_0000_0000_0000_0000_0001;
opcode= add;//3'b000
#10 $finish;
end
endmodule
I am confused as to why it says "wrong number of ports"? I assume it's the number of parameters in module alu and alu test_unit? They have the same number of parameters (a, b, c, opcode and overflow), so what exactly am I missing? How exactly do I get the value of overflow? It works fine before I added the overflow parameter, so I assume I'm doing it wrong?
For the second error, I read somewhere on here that it might be due to a missing declaration, but I have declared all of them... so I am not sure what's making it wrong.
I am not sure if this is the issue, but your module definition is not correct. It should be as follows:
module alu(
input signed[31:0] a,b,
input[3:0] opcode,
output signed[31:0] c,
output overflow
);
Perhaps this may help with your issue.
Commas separate inputs and outputs in the module declaration.
NEVER rely on the order of arguments to modules and ALWAYS try to use, for a module called A;
module A(output wire c,
input wire a,
input wire b);
...
endmodule // A
use an instance of it using;
A yourAname(.c(Bar),
.a(Foo1),
.b(Foo2));
so that if the definition and order of the I/O of the module changes, this instantiation will track those changes and/or give appropriate errors when simulated/synethesised.
You might find it useful to follow a few simple rules in your source code when naming;
inputs are denoted by i_yourinputname
outputs are denoted by o_youroutputname
inout are denoted by io_yourinputoutputname
wire are denoted by w_yourwirename
reg are denoted by r_yourregname
as this avoid confusion and is a good habit to get into as soon as possible when starting to learn verilog.
Referring to my previous post:
Error (10482): VHDL error: object "select_vector" is used but not declared
I converted my code from VHDL to verilog, but I'm getting this error now:
(Error (10734): Verilog HDL error at SWSelector.v(13): selector is not
a constant),
Any suggestions how do I deal with it? There are 8 possibilities for selector switch which are coming from a decoder. So whenever the value of selector matches 3'b000, I want rq to be assigned to requests. Here is my code:
module SWSelector(
input [7:0] rq,
input [2:0] selector,
output [7:0] request
);
localparam NUM=3'b000;
generate
genvar i;
for(i=0;i<7;i=i+1)
begin: label
if(selector == NUM)
begin
assign request[i] = rq[i];
end
else
begin
assign request[i]=0;
end
end
endgenerate
endmodule
Since your if-statement is in a generate, you're asking the tool to pre-evaluate what selector is set to in order to figure out selecter == NUM evaluates to, but your tool doesn't know because it's a signal, not a parameter.
You want to use the generate to create an always block that you can check the value of selector in, like so:
module SWSelector(
input [7:0] rq,
input [2:0] selector,
output reg [7:0] request
);
localparam NUM=3'b000;
generate
genvar i;
for(i=0;i<7;i=i+1)
begin: label
always #* begin
if(selector == NUM)
request[i] = rq[i];
else
request[i]=0;
end
end
endgenerate
endmodule
Or, as toolic said, you can use a ternary and an assign.
Edit:
Without generate:
module SWSelector(
input [7:0] rq,
input [2:0] selector,
output reg [7:0] request
);
localparam NUM=3'b000;
integer i;
always #* begin
for(i=0;i<7;i=i+1)
if(selector == NUM)
request[i] = rq[i];
else
request[i]=0;
end
endmodule
I'm attempting to write a ripple carry adder in verilog.
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule
module full_adder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire t1,t2;
half_adder h(a,b,t1,t2);
assign cout=t1&cin;
assign sum=t1^cin;
assign cout=t2|cout;
endmodule // full_adder
module ripple_carry_adder(input1,input2,answer);
input [31:0] input1,input2;
output [31:0] answer;
integer carry,t;
genvar i;
initial begin
assign carry=1'b0;
end
for(i=0;i<=31;i=i+1)
begin
full_adder f(input1[i],input2[i],carry,answer[i],t);
assign carry=t;
end
endmodule
however when i compile using the iverilog simulator, the following error log shows up(repetitive errors removed) :
ripple_carry_adder.v:28: warning: Couldn't build unique name for unnamed generate block - using internal name $gen1
ripple_carry_adder.v:30: warning: Port 3 (cin) of full_adder expects 1 bits, got 32.
ripple_carry_adder.v:30: : Pruning (signed) 31 high bits of the expression.
ripple_carry_adder.v:30: error: reg t; cannot be driven by primitives or continuous assignment.
ripple_carry_adder.v:30: error: Output port expression must support continuous assignment.
ripple_carry_adder.v:30: : Port cout of full_adder is connected to t
ripple_carry_adder.v:31: error: reg carry; cannot be driven by primitives or continuous assignment.
ripple_carry_adder.v:28: warning: Couldn't build unique name for unnamed generate block - using internal name $gen1
ripple_carry_adder.v:30: warning: Port 3 (cin) of full_adder expects 1 bits, got 32.
ripple_carry_adder.v:30: : Pruning (signed) 31 high bits of the expression.
ripple_carry_adder.v:30: error: reg t; cannot be driven by primitives or continuous assignment.
ripple_carry_adder.v:30: error: Output port expression must support continuous assignment.
ripple_carry_adder.v:30: : Port cout of full_adder is connected to t
ripple_carry_adder.v:31: error: reg carry; cannot be driven by primitives or continuous assignment.
Where am I going wrong?
EDIT: Using the generate statement now.Still have doubt about the type of carry.
module ripple_carry_adder(input1,input2,answer);
input [31:0] input1,input2;
output [31:0] answer;
wire carry;
wire t;
initial begin
carry=1'b0;
end
genvar i;
generate for(i=0;i<=31;i=i+1)
begin
full_adder f(input1[i],input2[i],carry,answer[i],t);
carry=t;
end endgenerate
endmodule
You should get rid of the initial block. You can drop t. Then using an generate block:
wire [31:0] carry;
genvar i;
full_adder f(input1[0],input2[0],1'b0,answer[0],carry[0]);
generate // optional in IEEE std 1364-2005 and IEEE std 1800
for(i=1;i<=31;i=i+1)
begin
full_adder f(input1[i],input2[i],carry[i-1],answer[i],carry[i]);
//assign carry=t;
end
endgenerate
endmodule
Alternatively, something that worked with the old 1364-1995 style:
full_adder f[31:0](input1[31:0],input2[31:0],{carry[30:0],1'b0},answer[31:0],carry[31:0]);
assign statements are not to be used inside of statement blocks. Anytime you have a begin/end block, the left-hand side of the statement gets set without using the assign keyword. e.g.:
initial begin
carry = 1'b0
end
You cannot instantiate modules inside a procedural block or for-loop (e.g. full_adder), you need to use a generate statement instead. You declared a genvar, so I think you meant to do this, but you don't seem to have the generate statement.
You cannot drive a reg/integer type from the output of a module, reg/integers can only be driven from a procedural block. Change type t from an integer to a wire[31:0] instead.