I would like to write a test for FPU module and can't find out a way to change a rounding mode of real numbers in SystemVerilog. Does the system function or any easy method exist to do that?
Thank you in advanced
There's no way to change the rounding mode (away from 0). You can choose to truncate using the $rtoi function, or look at the bit patterns directly using $realtobits.
I think you should send this out to a C environment via DPI, where you should be able to have more precise control over the rounding mode in use.
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I am writing a driver for a DDS(AD9959, analog devices) chip in python. Some of the modes written in the datasheet require writing the register bits as do not care. What is the correct way to implement the same? I tried to use 'x', but the bits are not being written on the chip.
The term "don't care" does not mean some special value for a bit. A bit can only be 0 or 1.
When reading it means that you can ignore the value. Commonly you mask it away.
When writing it means that you are free to choose any value. Most developers write a 0.
I look for some standard which defines some table, which first column contains key (what we see on keyboard (;:ж)(fа)(+=)) and second one contains numeric representation of this key. Does this standard exist?
Also I look for standard which connects Unicode(or at least ASCII) symbols and their numeric representation ((yeah, it is UTF-8/-16/etc) but in code I need to define what the symbol user has written by his keyboard, and different libs (in JS, or Xlib for Unix-systems) do it definitely differently, but I even do not know how).
It seems a bit weird and stupid, but my final target is get keycode from keyboard and calculate the symbol. Please make it clear for me!
P.S. Sorry for my english, thank you in advance!
Probably, there are no standards like what I need. There are several half-standards intended by different companies which product keyboards, but they are not what I need.
What is the effect of configuring a pull mode on a pin designated as output in the synthesis?
Does the pull mode still take effect?
Is its use only apparent if we set the output to tristate?
See the example below with a Lattice Diamond tool, I am able to configure the pull mode for an output.
It only has an effect on the output when the pin is in tristate. If you configure a weak pullup, I assume it burns some power if you drive the output low, and vice versa for weak pulldowns.
I prefer to configure an explicit IO buffer in order to make the tristate control explicit, but that is just a stylistic preference.
I2S specifications provide different modes of operation. I tried looking for advantages of one mode over the other but could not find any good literature. Can anyone provide or explain the advantage of one mode over the other ?
With samples that are aligned to the most significant bit, the sample length does not matter (because if the sent and expected sample lengths differ, any ignored or read-as-zero bits are the LSBs).
Otherwise, all choices are arbitrary and do not have any advantage whatsoever over each other.
(This is why hardware designers choose one I²S mode at random, instead of selecting an obviously best mode.)
Good day,
I am working on a Stratix III FPGA which contains M9K block memories, the contents of which are conveniently initialised to zero on power-on. This suits my application very well.
Is there a way to reset the contents back to zero without power-cycling/reflashing/etc the FPGA? There seems to be no such option in the megawizard plugin manager, and I would like to avoid wasting a bunch of logic which just goes and sequentially writes zero to every address...
I have looked around and there is no reference to such a mechanism, but I thought I'd ask just in case someone knew a handy trick :] By the way I'm working in VHDL but I should be able to translate any Verilog.
Datasheet (does not contain the answer!) : http://www.altera.com/literature/hb/stx3/stx3_siii51004.pdf
Thanks in advance,
- Thomas
PS: This be my first post here, so if I've violated any etiquette please let me know :)
Sorry, the conventional ways to do that are:
to re-configure the fpga (you could trigger that from within your hardware if you don;t mind the whole thing "disappearing" while it reconfigures)
explicitly write zeros in (as you already suggested)
At the wackier end of the solution space, I guess you could also wire something up to the JTAG port if you already have a microcontroller either in the FPGA or outside - you might be able to overwrite the RAM contents that way too.