I am trying to create a 4 bit counter using D flip flops in Verilog. I am following this diagram http://i.imgur.com/VR5593a.png. I got the code for the individual D flip flop. The problem I am having is with D0 in the first clock cycle. I am guessing I have to assume Q0 to be 1 and Q1, Q2, Q3 to be 0 at first. I am not sure how to pass the initial value for D0 only once in the code.
module DFlipFlop(CLK, D, Q);
input CLK, D;
output Q;
reg Q;
always #(posedge CLK) begin
Q <= D;
end
endmodule
module RippleMod(CLK, q0, q1, q2, q3);
input CLK;
output q0, q1, q2, q3;
DFlipFlop d1 (CLK,q3,q0);//not sure about q3 there, think I will get X if i do this.
DFlipFlop d2 (CLK,q0,q1);
DFlipFlop d3 (CLK,q1,q2);
DFlipFlop d4 (CLK,q2,q4);
endmodule
Using a reset signal will help you. So you just need to reset Q3 to 1 and the rest of the signals to 0.
You need to do something to set the initial state.
For simulation you can generally use "initial" blocks to set the initial state of registers. Some synthesis tools, especially those targeting FPGAs/CPLDs also support setting initial states in this way. Some synthesis tools that do not support initial blocks may support a tool-specific way of setting initial conditions.
The other option is to build a reset line into your flip-flops. The downside of this is of course that you then need something to trigger the reset line, either your testbench in simulation or some kind of hardware in a real implementation.
verilog initializes all 4-state variables to 'x'. so, you would run an 'x' around the loop forever without any real change. You need to provide an input to your case. something like the following (in SV)
module RippleMod(CLK, en, in, q0, q1, q2, q3);
input CLK, en, in;
output q0, q1, q2, q3;
logic d1in;
always_ff #(negedge clk) begin
if (en)
d1in <= in;
else
d1in <= q3;
end
DFlipFlop d1 (CLK,d1in,q0);
DFlipFlop d2 (CLK,q0,q1);
DFlipFlop d3 (CLK,q1,q2);
DFlipFlop d4 (CLK,q2,q4);
endmodule
At first you need to initialise the ring counter otherwise output remains in undefined state xxxx. Try out below code, where ffs are explicitly are initialised using an asynchronous load signal...
module shiftreg;
reg [3:0] in;
output [3:0] q;
reg clk, ld, rst;
dff D0 (q[3], clk, rst, 1'b1, q[0]);
dff D1 (q[0], clk, rst, 1'b0, q[1]);
dff D2 (q[1], clk, rst, 1'b0, q[2]);
dff D3 (q[2], clk, rst, 1'b0, q[3]);
initial clk = 0;
initial forever #5 clk = ~clk;
initial begin
$monitor($time, "ld = %b q = %b", ld, q);
#100 $finish;
end
endmodule
module dff (d, clk, rst, ld, q);
input d, clk, ld, rst;
output reg q;
initial if (ld) q <= 1; else q <=0;
always # (posedge clk)
if (rst == 1)
q <= 0;
else q <=d;
endmodule
Related
I've been designing a one-shot as part of my EE senior project and am unable to get the 'Reset' to toggle the output to 0.
I used the RTL_viewer in Quartus and the design does match my code: The DFF output (Q) is fed into 2 inverters then into the DFF Reset.
My understanding is that the two inverters should act as buffers. The DFF output should be 0 until the next clock edge is reached. I'm not sure if something is wrong with my design or if this is a timing error. I tried playing around with the clock speed and the buffer delay, but neither produced the correct results.
module oneShot(Clk, Q, Q_bar);
input Clk;
output Q, Q_bar;
logic X, Reset /* synthesis keep */;
logic D = 1'b1;
parameter propogation_delay = 30ns;
not #(propogation_delay) (X, Q);
not #(propogation_delay) (Reset, X);
//instantiation of flip flop
//DFF (Clk, Reset, D, Q);
DFF1 unit0 (Clk, Reset, D, Q);
assign Q_bar = ~ Q;
endmodule
module DFF1 (Clk, Reset, D, Q);
input Clk, Reset, D;
output logic Q;
always_ff #(posedge Clk)
begin
if(Reset == 1'b1)
Q <= 0;
else
Q <= D;
end
endmodule
module oneShot_tb;
logic Clk, Q, Q_bar, Reset;
oneShot DUT (Clk, Q, Q_bar);
always begin
Clk = 0;
#10;
Clk = 1'b1;
#10;
end
initial begin
#300;
$stop;
end
I have written the testbench code and design code for Master-slave JK flip flop, but output isn't coming.
Please point out the error.
Test bench.sv
module JK_ff_tb;
reg clk;
reg reset;
reg j,k;
wire q;
wire qb;
jk_flip_flop_master_slave jkflipflop( .clk(clk), .reset(reset), .j(j), .k(k), .q(q), .q_bar(qb) );
initial begin
$dumpfile("dump.vcd"); $dumpvars;
$monitor(clk,j,k,q,qb,reset);
j = 1'b0;
k = 1'b0;
reset = 1;
clk=1;
#10
reset=0;
j=1'b1;
k=1'b0;
#100
reset=0;
j=1'b0;
k=1'b1;
#100
reset=0;
j=1'b1;
k=1'b1;
#100
reset=0;
j=1'b0;
k=1'b0;
#100
reset=1;
j=1'b1;
k=1'b0;
end
always #25 clk <= ~clk;
endmodule
Design.sv
module jk_flip_flop_master_slave(j,k,clk,reset,q,q_bar);
input j,k,clk,reset;
output q,q_bar;
reg q,q_bar; // Active low reset signal.
wire MQ; // The master's Q output.
wire MQn; // The master's Qn output.
wire Cn; // The clock input to the slave shall be the complement of the master's.
wire J1;
wire K1;
wire J2; // The actual input to the first SR latch (S).
wire K2; // The actual input to the first SR latch (R).
assign J2 = !reset ? 0 : J1; // Upon reset force J2 = 0
assign K2 = !reset ? 1 : K1; // Upon reset force K2 = 1
and(J1, j, q_bar);
and(K1, k, q);
not(Cn, clk);
sr_latch_gated master(MQ, MQn, clk, J2, K2);
sr_latch_gated slave(q, q_bar, Cn, MQ, MQn);
endmodule // jk_flip_flop_master_slave
Sr_Latched flip flop module
module sr_latch_gated(Q, Qn, G, S, R);
output Q;
output Qn;
input G;
input S;
input R;
wire S1;
wire R1;
and(S1, G, S);
and(R1, G, R);
nor(Qn, S1, Q);
nor(Q, R1, Qn);
endmodule // sr_latch_gated
I have coded the entire thing in EDA-playground.
The diagram generated was really abrupt as well.
If there is another logic that can be implemented easily, do tell.
I get compile errors on 2 different simulators. You should not declare q and q_bar as reg in the jk_flip_flop_master_slave module. You should delete this line:
reg q,q_bar; // Active low reset signal.
Then it compiles and simulates for me. I see this output:
100xx1
110xx0
010010
110010
010010
110010
101010
001010
101010
001010
...
It is a simple asynchronous 2 bit counter, two JK flipflops are being used.
Here is my TwoBitCounter.v script.
`timescale 1ns / 1ps
module TwoBitCounter(
input wire clk,
output wire q0,
output wire q1
);
JK jk1(1, 1, clk, q0);
JK jk2(1, 1, q0, q1);
endmodule
module JK(
input wire J,
input wire K,
input wire clk,
output reg out
);
always #(posedge clk) begin
if(J==0&&K==0)
begin end
else if(J==0&&K==1) begin
out <= 1'b0;
end else if(J==1&&K==0) begin
out <= 1'b1;
end else if(J==1&&K==1) begin
out <= ~out;
end
end
endmodule
and this is my simulation code :
`timescale 1ns / 1ps
module TwoBitCounter_sim();
reg clk;
wire q0;
wire q1;
TwoBitCounter twoBitCounter(.clk(clk), .q0(q0));
initial clk = 1'b0;
always clk = #100 ~clk;
initial begin
#1000;
$finish;
end
endmodule
I have checked that JK module works properly alone. I tried disabling one JK flip flop to see if it has no errors while implemented in TwoBitCounter module, and it also did not work. Although I have checked several times to see if the algorithm itself is wrong, but got no clue what the fundamental problem is.
In your code there is only one J/K combination which you use: 1/1. In this state you just invert the out (out <= ~out). However you had never initialized it. Your out initially has x value. Inversion of x is also x. So, it never changes.
You need to figure out a way to initialize the flops either by manipulating J/K values or by other means.
As an example, adding initial out = 0; in the JK module will change the picture, but it will not play well with synthesis. So, you need to figure out your own way.
I am a beginner in designing circuit using verilog in modelsim. I use a sample code and a tutorial to learn how modelsim works. The code and the testbench are compiled without any problem and even testbench is simulated without any error but the input and output signals are not shown in object windows and they are not under instance menu. please describe for me how can I find them and simulate the waveforms.
here is my code and the test bench.
the definition of a D flipflop
// module D_FF with synchronous reset
module D_FF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
// Lots of new constructs. Ignore the functionality of the
// constructs.
// Concentrate on how the design block is built in a top-down fashion.
always #(negedge clk or posedge reset)
if (reset)
q <= 1'b0;
else
q <= d;
endmodule
the definition of a T flipflop from D
module T_FF(q, clk, reset);
output q;
input clk, reset;
wire d;
D_FF dff0(q, d, clk, reset);
not n1(d, q);
endmodule
counter codes:
module rcc4(q, clk, reset);
output [3:0] q;
input clk, reset;
//4 instances of the module T_FF are created.
T_FF tff0(q[0],clk, reset);
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule
testbench code:
module stimulus();
reg clk;
reg reset;
wire[3:0] q;
// instantiate the design block
rcc4 r1(q, clk, reset);
// Control the clk signal that drives the design block. Cycle time = 10
initial
clk = 1'b0; //set clk to 0
always
#5 clk = ~clk; //toggle clk every 5 time units
// Control the reset signal that drives the design block
// reset is asserted from 0 to 20 and from 200 to 220.
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish; //terminate the simulation
end
// Monitor the outputs
initial
$monitor($time, " Output q = %d", q);
endmodule
I am using modelsim 10.1c on Windows 10.
The following picture is from my project and it shows my object and instance window.
The switch -voptargs=+acc will solve your issue.
vsim -voptargs=+acc modulename
I'm trying to design a 4-bit counter with T-flipflop, here's what i did:
1- From a D-flipflop to T-flipflop:
module T_FlipFlop( clk,T, Q);
input wire clk;
input wire T;
output reg Q;
wire D;
initial
begin
Q<=1'b0;
end
assign D= T ^ Q;
always #(negedge clk)
begin
Q<=D;
end
endmodule
with RTL shematic :
following this "D_ff to T_ff" conversion:
2- Then, i instantiated 4 T-flipflops in the top module and connected the output of each flipflop to the clk of the next one:
module Counters_FreqDividers( sysclk,Q1,Q2,Q3,Q4);
input sysclk;
output wire Q1;
output wire Q2;
output wire Q3;
output wire Q4;
T_FlipFlop num_1(.clk(sysclk),.T(1'b1),.Q(Q1));
T_FlipFlop num_2(.clk(Q1),.T(1'b1),.Q(Q2));
T_FlipFlop num_3(.clk(Q2),.T(1'b1),.Q(Q3));
T_FlipFlop num_4(.clk(Q3),.T(1'b1),.Q(Q4));
endmodule
with RTL schematic :
to follow this diagram:
We know that T-flipflop is just a JK-flipflop with J and K connected to each other and that's what we have here, so consider them as T-flipflops.
3-The simulation:
4- Finally, my questions:
1) why Q1 is the ONLY output that operates properly?
2) Why Q2, Q3, Q4 starts with 1 although i have initialized them as 0?
I can't figure out what's missing, i tried to play around but nothing worked and i'm stuck here!
Edit: my testbench:
module test;
// Inputs
reg sysclk;
// Outputs
wire Q1;
wire Q2;
wire Q3;
wire Q4;
// Instantiate the Unit Under Test (UUT)
Counters_FreqDividers uut (
.sysclk(sysclk),
.Q1(Q1),
.Q2(Q2),
.Q3(Q3),
.Q4(Q4)
);
initial begin
// Initialize Inputs
sysclk <= 1'b1;
#200 $finish();
end
always #5 sysclk=~sysclk;
endmodule