I am designing Signed comparator that uses the unisgned comparator module. i.e. if A and B are 4 bit vectors and
if A[3] ==1 and B[3]==0 then
Gout = 0, Eout = 0 and Lout = 1.
if A[3]==0 and B[3]==1 then
Gout = 1, Eout = 0 and Lout = 0;
else if both A[3] and B[3] are same then
the unisigned comparator module has to be instantiated.
How can I write this gate instantiation inside a if else statement?
module SCOMP(A,B,Great_in,Equal_in,Less_in,Great_out,Equal_out,Less_out);
input[3:0] A;
input[3:0] B;
input Great_in,Equal_in,Less_in;
output Great_out,Equal_out,Less_out;
reg[3:0] X;
reg[3:0] Y;
reg p,q,r;
wire x,y,z;
initial
begin
X = 0000& A[2:0];
Y = 0000& B[2:0];
end
COMP4 g1(X,Y,Gin,Ein,Lin,x,y,z);
always #(*)
begin
if ((A[3]==0)&& (B[3]==1))
begin
assign p = 1;
assign q = 0;
assign r =0;
end
else if ((A[3]== 1)&&(B[3]==0))
begin
assign p = 0;
assign q = 0;
assign r = 1;
end
else
begin
assign p = x;
assign q = y;
assign r = z;
end
end
assign Great_out = p;
assign Equal_out = q;
assign Less_out = r;
endmodule
Verilog is a Hardware Description Language. Hardware either exists or it doesn't. Instantiation of anything is like soldering a chip to a PCB. Instantiating something inside an if statement would be like designing a PCB where the chips can magically appear or disappear depending on some input to the PCB.
Your "unsigned comparator module" has to exist for all time - it has to be instantiated unconditionally. You then need to use your if statements to decide whether to use the outputs from this "unsigned comparator module" or to ignore them, eg:
// the instance of the "unsigned comparator module"
unsigned_comparator_module UCM ( ... .gout(ucm_gout), .eout(ucm_eout), .lout(ucm_lout) ... );
always #* begin
if (A[3] == 1 && B[3] == 0) begin
Gout = 0; Eout = 0; Lout = 1;
end else if (A[3] == 0 && B[3] == 1) begin
Gout = 1; Eout = 0; Lout = 0;
end else if (A[3] == B[3]) begin
Gout = ucm_gout; Eout = ucm_eout; Lout = ucm_lout;
end
end
the best way to do that inside the if condition write the comparator code where u want. for eaxample
else if both A[3] and B[3] are same then
the unisigned comparator module has to be written here.
Related
I have been trying to make an asynchronous fifo in verilog but I'm facing a problem of object "empty" and "full" on left side of assignment should have variable data type.
Top module:
module async_fifo (reset, wclock, rclock, datain, dataout, e, f);
input [15:0] datain;
output reg [15:0] dataout;
//reg [15:0] mem1, mem2, mem3, mem4, mem5, mem6, mem7, mem8;
reg [15:0] mem [7:0];
input reset, rclock, wclock;
/*reg [0:2] wptr, rptr;
initial wptr = 3'b000;
initial rptr = 3'b000;*/
integer wflag = 0, rflag = 0;
wire empty , full;
input e,f;
reg [0:2] wptr = 3'b000, rptr = 3'b000;
counter c(wclock, rclock, empty, full);
e = empty;
f = full;
always#(posedge wclock)
begin
if(f == 1'b0)
begin
e = 1'b0;
if (wptr < 3'b111)
begin
mem[wptr] = datain;
wptr = wptr + 3'b001;
end
else if(wptr == 3'b111 && wflag == 0)
wflag = 1;
else if (wflag == 1)
begin
wptr = 3'b000;
wflag = 0;
end
end
end
always#(posedge rclock)
begin
if(e == 1'b0)
begin
f = 1'b0;
if (rptr < 3'b111)
begin
dataout = mem[rptr];
rptr = rptr + 3'b001;
end
else if(rptr == 3'b111 && rflag == 0)
rflag = 1;
else if (rflag == 1)
begin
rptr = 3'b000;
rflag = 0;
end
end
end
endmodule
Counter module:
module counter(w_clock, r_clock, empty, full);
input w_clock, r_clock;
output reg empty = 0, full = 0;
integer rear = 0, front = 0;
always # (posedge w_clock)
begin
if ((front == 1 && rear == 8) || front == rear + 1)
full = 1;
else if(rear == 8)
begin
rear = 1;
empty = 0;
end
else
begin
rear = rear+1;
empty = 0;
end
end
always # (posedge r_clock)
begin
if (front == 0 && rear == 0)
empty = 1;
else if(front == 8)
begin
front = 1;
full = 0;
end
else
begin
front = front+1;
full = 0;
end
end
endmodule
You are using full and empty in left hand side of behavioral block (always). So they have to be registers.
But at the same time they are output of counter and have to be wires.
You can't use variables in that way.They can either be output of an instant and only used in right hand side of other parts of code or be regsietrs for using in left hand side of behavioral blocks that can also be input of another instant.
You better change your coding style.
Here is an examole of async FIFO:
http://www.asic-world.com/code/hdl_models/aFifo.v
And also you need to study about blocking & nonblocking assignment and race conditions. Take a look at this:
http://ee.hawaii.edu/~sasaki/EE361/Fall01/vstyle.txt
I am working on designing a finite state machine in Verilog to represent a stack. The module is as follows:
module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err);
input [2:0] s;
input Enable, Clock, Resetn;
output reg [1:0] c;
output reg OF_Err = 0, UF_Err = 0;
reg [2:0] y, Y;
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;
always #(s, y, Enable)
if (Enable)
begin
case (y)
A: if (s == 3'b000) Y = B;
else
begin
Y = A;
UF_Err = 1;
end
B: if (s == 3'b000) Y = C;
else if (s == 3'b001) Y = A;
else
begin
Y = B;
UF_Err = 1;
end
C: if (s == 3'b000) Y = D;
else if (s == 3'b100) Y = C;
else Y = B;
D: if (s == 3'b000) Y = E;
else if (s == 3'b100) Y = D;
else Y = C;
E: if (s == 3'b000)
begin
Y = E;
OF_Err = 1;
end
else if (s == 3'b100) Y = E;
else Y = D;
default: Y = 3'bxxx;
endcase
c[1] = y[1];
c[0] = y[0];
end
always #(negedge Resetn, posedge Clock)
begin
if (Resetn == 0)
begin
y <= A;
OF_Err = 0; //Problem
UF_Err = 0; //Problem
end
else y <= Y;
end
OF_Err and UF_Err are indicators of overflow and underflow errors, respectively.
However, I get the following errors when compiling my project:
Error (10028): Can't resolve multiple constant drivers for net "OF_Err" at state_machine.v(59)
Error (10029): Constant driver at state_machine.v(10)
Error (10028): Can't resolve multiple constant drivers for net "UF_Err" at state_machine.v(59)
These only appeared after I added the commented lines. I want to reset the over- and underflow indicators when the FSM is reset, but I can't do it the way I have it. How do I go about doing this?
(If it's of any value, this is to be executed on an Altera DE2-115).
In two always blocks you have assigned the values to OF_Err and UF_Err. This is the reason it is showing multiple constant driver error.
module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err);
input [2:0] s;
input Enable, Clock, Resetn;
output reg [1:0] c;
output OF_Err, UF_Err; //modified
reg [2:0] y, Y;
reg of_Err, uf_Err; //added
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E =3'b100;
always #*
begin
if (Enable)
begin
case (y)
A: if (s == 3'b000)
Y = B;
else
begin
Y = A;
uf_Err = 1; //modified
end
B: if (s == 3'b000)
Y = C;
else if (s == 3'b001)
Y = A;
else
begin
Y = B;
uf_Err = 1; //modified
end
C: if (s == 3'b000)
Y = D;
else if (s == 3'b100)
Y = C;
else
Y = B;
D: if (s == 3'b000)
Y = E;
else if (s == 3'b100)
Y = D;
else Y = C;
E: if (s == 3'b000)
begin
Y = E;
of_Err = 1; //modified
end
else if (s == 3'b100) Y = E;
else Y = D;
default: Y = 3'bxxx;
endcase
c[1] = y[1];
c[0] = y[0];
end
else
begin
//write the condition if the Enable signal is not high.I guess you're trying to synthesize
end
end
always #(negedge Resetn, posedge Clock)
begin
if (Resetn == 0)
begin
y <= A;
// OF_Err = 0; //Problem
// UF_Err = 0; //Problem
end
else y <= Y;
end
assign OF_Err = !Resetn? of_Err : 1'b0; //added
assign UF_Err = !Resetn? uf_Err : 1'b0; //added
endmodule
As others have already pointed out, OF_Err and UF_Err were driver by two always blocks which is illegal for synthesis. I recommend creating two additional variables of_Err and uf_Err like Arvind suggested. However I recommend keeping OF_Err and UF_Err as flops.
The if (Enable) in the combinational block infers Y,c and the *_Err as level-sensitive latches. I highly doubt this is what you intendeds. I recommend moving the if (Enable) into synchronous always block and keeping the combinational logic as pure combinational.
c is a simple assignment, so it might make more sense having it as a wire instead of a reg with a simple assign statement. It can be in the combinational block, but I prefer to separate combinational input from output.
You did use #(s, y, Enable) correctly, however #* or the synonymous #(*) is recommenced for combinational block. #* is an auto sensitivity list which saves you typing, maintenance, and removes the risk of forgetting a signal.
always #*
begin
of_Err = OF_Err; // <-- default values
uf_Err = UF_Err;
case (y)
// ... your original case code with OF_Err/UF_Err renamed to of_Err/uf_Err
endcase
end
always #(posedge Clock, negedge Resetn) // style difference, I prefer the clock to be first
begin
if (Resetn == 1'b0)
begin
y <= A;
OF_Err <= 1'b0;
UF_Err <= 1'b0;
end
else if (Enable)
begin
y <= Y;
OF_Err <= of_Err;
UF_Err <= uf_Err;
end
end
assign c[1:0] = y[1:0];
Because OF_Err and UF_ERR are driven by multiple always blocks.
A reg should be driven by only one always block. And if it is having
multiple drivers by design, then it should be a wire.
Here is your modified code.
module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err);
input [2:0] s;
input Enable, Clock, Resetn;
output reg [1:0] c;
output reg OF_Err = 0, UF_Err = 0;
reg [2:0] y, Y;
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;
always #(s, y, Enable, negedge reset)
begin
if (!reset)
begin
OF_Err = 0; //Problem
UF_Err = 0; //Problem
end
else
begin
if (Enable)
begin
case (y)
A: if (s == 3'b000) Y = B;
else
begin
Y = A;
UF_Err = 1;
end
B: if (s == 3'b000) Y = C;
else if (s == 3'b001) Y = A;
else
begin
Y = B;
UF_Err = 1;
end
C: if (s == 3'b000) Y = D;
else if (s == 3'b100) Y = C;
else Y = B;
D: if (s == 3'b000) Y = E;
else if (s == 3'b100) Y = D;
else Y = C;
E: if (s == 3'b000)
begin
Y = E;
OF_Err = 1;
end
else if (s == 3'b100) Y = E;
else Y = D;
default: Y = 3'bxxx;
endcase
c[1] = y[1];
c[0] = y[0];
end
end
end
always #(negedge Resetn, posedge Clock)
begin
if(Resetn == 0)
y <= A;
else
y <= Y;
end
I am somewhat new to verilog, I tried running this code but it gives me an error:
module enc(in,out);
input [7:0] in;
output [3:0] out;
reg i;
reg [3:0] out;
always #*
begin
for (i=0;i<7;i=i+1)
begin
if ((in[i]==1) && (in[7:i+1]==0))
out = i;
else
out = 0;
end
end
endmodule
I think it complains about in[7:i+1] but i don't understand why ?
Can someone please advise..
EDIT
ok so I am reluctant to using the X due to their numerous problems.. I was thinking of modifying the code to something like this :
module enc(in,out);
input [7:0] in;
output [2:0] out;
reg i;
reg [2:0] out,temp;
always #*
begin
temp = 0;
for (i=0;i<8;i=i+1)
begin
if (in[i]==1)
temp = i;
end
out = temp;
end
endmodule
Do you think that will do the trick ? I currently don't have access to a simulator..
A priority encoder mean giving priority to a one bit if two or more bits meet the criteria. Looking at your code, it appears you wanted to give priority to a LSB while using a up counter. out is assigned in every look, so even if your could compile, the final result would be 6 or 0.
For an LSB priority encoder, first start with a default value for out and use a down counter:
module enc (
input wire [7:0] in,
output reg [2:0] out
);
integer i;
always #* begin
out = 0; // default value if 'in' is all 0's
for (i=7; i>=0; i=i-1)
if (in[i]) out = i;
end
endmodule
If you are only interested in simulation than your linear loop approach should be fine, something like
out = 0;
for (i = W - 1; i > 0; i = i - 1) begin
if (in[i] && !out)
out = i;
end
If you also care about performance, the question becomes more interesting. I once experimented with different approaches to writing parameterized priority encoders here. It turned out that Synopsys can generate efficient implementation even from the brain-dead loop above but other toolchains needed explicit generate magic. Here is an excerpt from the link:
output [WIDTH_LOG - 1:0] msb;
wire [WIDTH_LOG*WIDTH - 1:0] ors;
assign ors[WIDTH_LOG*WIDTH - 1:(WIDTH_LOG - 1)*WIDTH] = x;
genvar w, i;
integer j;
generate
for (w = WIDTH_LOG - 1; w >= 0; w = w - 1) begin
assign msb[w] = |ors[w*WIDTH + 2*(1 << w) - 1:w*WIDTH + (1 << w)];
if (w > 0) begin
assign ors[(w - 1)*WIDTH + (1 << w) - 1:(w - 1)*WIDTH] = msb[w] ? ors[w*WIDTH + 2*(1 << w) - 1:w*WIDTH + (1 << w)] : ors[w*WIDTH + (1 << w) - 1:w*WIDTH];
end
end
endgenerate
So my Edited solution worked... how silly !! I forgot to declare reg [2:0] i; and instead wrote reg i;
Thanks everybody
Hunks, I have to tell you, all your solutions are either too complex or non-synthesizable, or implement into slow multiplexors. Alexej Bolshakov at OpenCores uploaded an outstandin' parametrizable encoder on Aug 23, 2015, based on OR elements. No muxes, 100% synthesizable. His code (with my tiny formatting):
module encoder #(
parameter LINES = 16,
parameter WIDTH = $clog2(LINES)
)(
input [LINES-1:0] unitary_in,
output wor [WIDTH-1:0] binary_out
);
genvar i, j;
generate
for (i = 0; i < LINES; i = i + 1)
begin: loop_i
for (j = 0; j < WIDTH; j = j + 1)
begin: loop_j
if (i[j])
assign binary_out[j] = unitary_in[i];
end
end
endgenerate
endmodule
RTL viewer screenshot, Model-Sim screenshot
This solution divides the input into four blocks and checks for the first nonzero block. This block is further subdivided in the same way. It is reasonably efficient.
// find position of most significant 1 bit in 64 bits input
// (system verilog)
module bitscan(
input logic [63:0] in, // number input
output logic [5:0] out, // bit position output
output logic zeroout // indicates if input is zero
);
logic [63:0] m0; // intermediates
logic [15:0] m1;
logic [3:0] m2;
logic [5:0] r;
always_comb begin
m0 = in;
// choose between four 16-bit blocks
if (|m0[63:48]) begin
m1 = m0[63:48];
r[5:4] = 3;
end else if (|m0[47:32]) begin
m1 = m0[47:32];
r[5:4] = 2;
end else if (|m0[31:16]) begin
m1 = m0[31:16];
r[5:4] = 1;
end else begin
m1 = m0[15:0];
r[5:4] = 0;
end
// choose between four 4-bit blocks
if (|m1[15:12]) begin
m2 = m1[15:12];
r[3:2] = 3;
end else if (|m0[11:8]) begin
m2 = m1[11:8];
r[3:2] = 2;
end else if (|m0[7:4]) begin
m2 = m1[7:4];
r[3:2] = 1;
end else begin
m2 = m1[3:0];
r[3:2] = 0;
end
// choose between four remaining bits
if (m2[3]) r[1:0] = 3;
else if (m2[2]) r[1:0] = 2;
else if (m2[1]) r[1:0] = 1;
else r[1:0] = 0;
out = r;
zeroout = ~|m2;
end
endmodule
Here is another solution that uses slightly less resourcess:
module bitscan4 (
input logic [63:0] in,
output logic [5:0] out,
output logic zout
);
logic [63:0] m0;
logic [3:0] m1;
logic [3:0] m2;
logic [5:0] r;
always_comb begin
r = 0;
m0 = in;
if (|m0[63:48]) begin
r[5:4] = 3;
m1[3] = |m0[63:60];
m1[2] = |m0[59:56];
m1[1] = |m0[55:53];
m1[0] = |m0[51:48];
end else if (|m0[47:32]) begin
r[5:4] = 2;
m1[3] = |m0[47:44];
m1[2] = |m0[43:40];
m1[1] = |m0[39:36];
m1[0] = |m0[35:32];
end else if (|m0[31:16]) begin
r[5:4] = 1;
m1[3] = |m0[31:28];
m1[2] = |m0[27:24];
m1[1] = |m0[23:20];
m1[0] = |m0[19:16];
end else begin
r[5:4] = 0;
m1[3] = |m0[15:12];
m1[2] = |m0[11:8];
m1[1] = |m0[7:4];
m1[0] = |m0[3:0];
end
if (m1[3]) begin
r[3:2] = 3;
end else if (m1[2]) begin
r[3:2] = 2;
end else if (m1[1]) begin
r[3:2] = 1;
end else begin
r[3:2] = 0;
end
m2 = m0[{r[5:2],2'b0}+: 4];
if (m2[3]) r[1:0] = 3;
else if (m2[2]) r[1:0] = 2;
else if (m2[1]) r[1:0] = 1;
else r[1:0] = 0;
zout = ~|m2;
out = r;
end
endmodule
To be able to use variable indexes in part-slice suffixes, you must enclose the for block into a generate block, like this:
gen var i;
generate
for (i=0;i<7;i=i+1) begin :gen_slices
always #* begin
... do whatever with in[7:i+1]
end
end
The problem is that apllying this to your module, the way it's written, leads to other errors. Your rewritten module would look like this (be warned: this won't work either)
module enc (
input wire [7:0] in,
output reg [2:0] out // I believe you wanted this to be 3 bits width, not 4.
);
genvar i; //a generate block needs a genvar
generate
for (i=0;i<7;i=i+1) begin :gen_block
always #* begin
if (in[i]==1'b1 && in[7:i+1]=='b0) // now this IS allowed :)
out = i;
else
out = 3'b0;
end
end
endgenerate
endmodule
This will throw a synthesis error about out being driven from more than one source. This means that the value assigned to out comes from several sources at the same time, and that is not allowed.
This is because the for block unrolls to something like this:
always #* begin
if (in[0]==1'b1 && in[7:1]=='b0)
out = 0;
else
out = 3'b0;
end
always #* begin
if (in[1]==1'b1 && in[7:2]=='b0)
out = 1;
else
out = 3'b0;
end
always #* begin
if (in[2]==1'b1 && in[7:3]=='b0)
out = 2;
else
out = 3'b0;
end
.... and so on...
So now you have multiple combinational block (always #*) trying to set a value to out. All of them will work at the same time, and all of them will try to put a specific value to out whether the if block evaluates as true or false. Recall that the condition of each if statement is mutually exclusive with respect of the other if conditions (i.e. only one if must evaluate to true).
So a quick and dirty way to avoid this multisource situation (I'm sure there are more elegant ways to solve this) is to let out to be high impedance if the if block is not going to assign it a value. Something like this:
module enc (
input wire [7:0] in,
output reg [2:0] out // I believe you wanted this to be 3 bits width, not 4.
);
genvar i; //a generate block needs a genvar
generate
for (i=0;i<7;i=i+1) begin :gen_block
always #* begin
if (in[i]==1'b1 && in[7:i+1]=='b0) // now this IS allowed :)
out = i;
else
out = 3'bZZZ;
end
end
endgenerate
always #* begin
if (in[7]) // you missed the case in which in[7] is high
out = 3'd7;
else
out = 3'bZZZ;
end
endmodule
On the other way, if you just need a priority encoder and your design uses fixed and small widths for inputs and outputs, you may write your encoder as this:
module enc (
input wire [7:0] in,
output reg [2:0] out
);
always #* begin
casex (in)
8'b1xxxxxxx : out = 3'd7;
8'b01xxxxxx : out = 3'd6;
8'b001xxxxx : out = 3'd5;
8'b0001xxxx : out = 3'd4;
8'b00001xxx : out = 3'd3;
8'b000001xx : out = 3'd2;
8'b0000001x : out = 3'd1;
8'b00000001 : out = 3'd0;
default : out = 3'd0;
endcase
end
endmodule
(although there seems to be reasons to not to use casex in a design. Read the comment #Tim posted about it in this other question: How can I assign a "don't care" value to an output in a combinational module in Verilog )
In conclusion: I'm afraid that I have not a bullet-proof design for your requirements (if we take into account the contents of the paper Tim linked in his comment), but at least, you know now why i was unallowed inside a part-slice suffix.
On the other way, you can have half of the work done by studying this code I gave as an answer to another SO question. In this case, the module works like a priority encoder, parametrized and without casex statements, only the output is not binary, but one-hot encoded.
How to parameterize a case statement with don't cares?
out = in&(~(in-1))
gives you the one-hot results(FROM LSB->MSB where the first 1 at)
I have a homework problem where I'm supposed to create a module for single-precision IEEE-754 floating point multiplication. This is the module:
module prob3(a, b, s);
input [31:0] a, b; // operands
output reg [31:0] s; // sum - Could potentially use wire instead
integer i; // loop variable
reg [8:0] temp;
reg [47:0] intProd; // intermediate product
reg [23:0] tempA;
reg [23:0] tempB;
initial begin
//Initialization
for (i = 0; i < 48; i = i + 1) begin
intProd[i] = 0;
end
//Compute the sign for the result
if (a[31]^b[31] == 0) begin
s[31] = 0;
end
else begin
s[31] = 1;
end
//Compute the exponent for the result
#10 temp = a[30:23] + b[30:23] - 8'b11111111;
//Case for overflow
if(temp > 8'b11111110) begin
s[30:23] = 8'b11111111;
for (i = 0; i < 23; i = i + 1) begin
s[i] = 0;
end
$finish;
end
//Case for underflow
else if (temp < 8'b00000001) begin
for (i = 0; i < 31; i = i + 1) begin
s[i] = 0;
end
$finish;
end
else begin
s[30:23] = temp[7:0];
end
//Mutliply the signficands
//Make implicit one explicit
tempA[23] = 1;
tempB[23] = 1;
//Make operands 24 bits
for(i = 0; i < 23; i = i + 1) begin
tempA[i] = a[i];
tempB[i] = b[i];
end
//Compute product of signficands
intProd = tempA * tempB;
//Check and see if we need to normalize
if(intProd[47:46] >= 2'b10) begin
intProd = intProd >> 1;
temp = s[30:23] + 1'b1;
if(temp > 8'b11111110) begin
s[30:23] = 8'b11111111;
for (i = 0; i < 23; i = i + 1) begin
s[i] = 0;
end
$finish;
end
else
s[30:23] = temp[7:0];
end
s[22:0] = intProd[47:25];
end
endmodule
Here is my testbench:
module prob4;
reg [31:0] a, b;
wire [31:0] s;
// instantiate the floating point multiplier
prob3 f1(a, b, s);
initial begin
assign a = 32'h42055555;
assign b = 32'hBDCCCCCD;
#10 $monitor("s = %h", s);
assign a = 32'hBF555555;
assign b = 32'hCAB71B00;
#10 $monitor("s = %h", s);
a = 32'hFF500000;
b = 32'h7E700000;
#10 $display("s = %b", s);
a = 32'h01700000;
b = 32'h02F00000;
#10 $display("s = %b", s);
a = 32'hBE000000;
b = 32'h455F36DB;
#10 $display("s = %b", s);
a = 32'h3C800000;
b = 32'h3A800000;
#10 $display("s = %b", s);
a = 32'hC797E880;
b = 32'hB7FBA927;
#10 $display("s = %b", s);
end
endmodule
It displays the first value of s, but that is it. I'm honestly not too familiar with Verilog, so any clarification on why this might be happening would be truly appreciated.
The reason you are seeing only a single value for s is because all of your floating point logic (all the stuff in the prob3 module) is inside an initial block. Thus, you only run that code once; it starts at time 0, has a pause for 10 time units and finishes; never to run again. Here are a few tips for implementing the unit (assuming the module is suppose to be synthesizable and not just a functional verification model):
Place your combinational logic in an always #(*) block, not an initial block.
As toolic mentioned, only call $monitor once, and it will inform you whenever s or any other variables given as arguments change; thus you do not need the $display statements either unless you want to know the value of s at that point of execution (whether it changed or not and inline with the processes, so not necessarily the final value either). So typically your testbench main stimulus initial block would have $monitor() as the first line.
Don't call $finish inside your logic; ideally, you should set an error signal instead that the testbench might then choose to call $finish if it sees that error signal asserted.
Don't use assign inside procedural blocks (always, initial, etc), just say a = ... not assign a = ...
So I'm trying to implement a basic ALU for my first Verilog course, DSD II. Xilinx keeps reporting an error on the lines where I call the gate primitives "and"/"or", but I've used them in previous assignments this way with no errors. Can anybody see what I'm missing?
Code:
module ALU(a,b, opcode, carry, Y, zeroflag);
input [15:0]a;
input [15:0]b;
input [3:0]opcode;
wire In = {opcode,a,b};
output reg carry;
output reg [15:0]Y;
output reg zeroflag;
always #(In)
begin
case(opcode)
//Zero Op
4'b0000 :
begin
Y = 16'h00;
carry = 0;
zeroflag = 1;
end
//Add
4'b0001:
begin
Ripple_Carry_Adder RCA1(Y,carry,a,b,carry);
end
//Subtract
4'b0010:
begin
end
//Multiply
4'b0011:
begin
Y = a*b;
if (Y > 65535)
carry = 1;
else
carry = 0;
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
//Divide
4'b0100:
begin
Y = a/b;
if (Y > 65535)
carry = 1;
else
carry = 0;
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
//And
4'b0110:
begin
and(Y, a, b);
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
//Or
4'b0111:
begin
or(Y,a,b);
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
//Zero Test
4'b1001:
if((a || b) == 0)
begin
Y = 0;
zeroflag = 1;
carry = 0;
end
//Greater Than
4'b1010:
begin
if(a > b)
Y = a;
else if (b > a)
Y = b;
else
Y = 16'h00;
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
//Equal
4'b1011:
begin
if (a == b)
Y = 16'h11;
else
Y = 16'h00;
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
//Less Than
4'b1100:
begin
if(a < b)
Y = a;
else if (b < a)
Y = b;
else
Y = 16'h00;
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
default :
begin
Y = 16'hxx;
carry = 1'bx;
zeroflag = 1'bx;
end
endcase
end
endmodule
You are instantiating the primitives (as well as the module Ripple_Carry_Adder) inside of an always block, which is not allowed.
Any time you create a module or primitive instance, think of it as placing down a physical piece of hardware. You cannot create it conditionally - it is always there.
So for something like an ALU design, you may want all the operations (add, sub, multiply, divide, etc.) to always happen, and then select the desired output depending on the opcode.