Getting a simple syntax error when using a gate primitive? - verilog

Question

So I'm trying to implement a basic ALU for my first Verilog course, DSD II. Xilinx keeps reporting an error on the lines where I call the gate primitives "and"/"or", but I've used them in previous assignments this way with no errors. Can anybody see what I'm missing?
Code:
module ALU(a,b, opcode, carry, Y, zeroflag);
input [15:0]a;
input [15:0]b;
input [3:0]opcode;
wire In = {opcode,a,b};
output reg carry;
output reg [15:0]Y;
output reg zeroflag;
always #(In)
begin
case(opcode)
//Zero Op
4'b0000 :
begin
Y = 16'h00;
carry = 0;
zeroflag = 1;
end
//Add
4'b0001:
begin
Ripple_Carry_Adder RCA1(Y,carry,a,b,carry);
end
//Subtract
4'b0010:
begin
end
//Multiply
4'b0011:
begin
Y = a*b;
if (Y > 65535)
carry = 1;
else
carry = 0;
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
//Divide
4'b0100:
begin
Y = a/b;
if (Y > 65535)
carry = 1;
else
carry = 0;
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
//And
4'b0110:
begin
and(Y, a, b);
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
//Or
4'b0111:
begin
or(Y,a,b);
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
//Zero Test
4'b1001:
if((a || b) == 0)
begin
Y = 0;
zeroflag = 1;
carry = 0;
end
//Greater Than
4'b1010:
begin
if(a > b)
Y = a;
else if (b > a)
Y = b;
else
Y = 16'h00;
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
//Equal
4'b1011:
begin
if (a == b)
Y = 16'h11;
else
Y = 16'h00;
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
//Less Than
4'b1100:
begin
if(a < b)
Y = a;
else if (b < a)
Y = b;
else
Y = 16'h00;
if (Y == 0)
zeroflag = 1;
else
zeroflag = 0;
end
default :
begin
Y = 16'hxx;
carry = 1'bx;
zeroflag = 1'bx;
end
endcase
end
endmodule

Answer 1

You are instantiating the primitives (as well as the module Ripple_Carry_Adder) inside of an always block, which is not allowed.
Any time you create a module or primitive instance, think of it as placing down a physical piece of hardware. You cannot create it conditionally - it is always there.
So for something like an ALU design, you may want all the operations (add, sub, multiply, divide, etc.) to always happen, and then select the desired output depending on the opcode.