Verilog State Machine with Pulse Counter - verilog

Question

Hey guys so I written two Verilog modules, one is a state machine and the other is a counter that generates a pulse every half second for the machine to count.I tried to make a a top level design that would instantiate both modules, however when running a test bench, my state outputs would always equal to 'xx'. Any advice or help please?
COUNTER/PULSE:
module pulseit(clk, reset, pulse);
input clk, reset;
output pulse;
reg [25:0] count;
wire pulse;
always # (posedge clk, posedge reset)
if (reset) count <= 26'b0; else
if (pulse) count <= 26'b0; else
count <= count + 26'b1;
endmodule
STATE MACHINE:
module sm(clk, reset, in, state, pulse);
input clk, reset, in, pulse;
output [1:0] state;
reg [1:0] state, nstate;
always # (posedge clk, posedge reset)
if (reset) state <= 2'b0;
else state <= nstate;
always # (*)
begin
nstate = state;
if (pulse)
begin
case(state)
2'b00: nstate = (in)? 2'b01:2'b11;
2'b01: nstate = (in)? 2'b10:2'b00;
2'b10: nstate = (in)? 2'b11:2'b01;
2'b11: nstate = (in)? 2'b00:2'b10;
endcase
end
end
endmodule
TOPLEVEL:
module topLevel(clk, rst, in, state);
input clk, rst, in;
output [1:0] state;
reg [1:0] state;
wire y;
pulseit pull (.clk(clk), .reset(rst), .pulse(y));
sm machine (.clk(clk), .reset(rst), .in(in), .state(state), .pulse(y));
endmodule

Answer 1

While writing a module, it is a good practice for designer to ensure that all the ports must be driven from module. There may be intentional some left-outs of connection, but the major ports must be connected.
Here wire y is connected as an output pulse of pulseit module. But the output pulse is never driven. The pulseit module just increments count and that too it is dependent on pulse signal. Also the FSM module entirely depends on the pulse signal it gets as an input.
pulse needs to be driven by some logic inside pulseit module. I modified the pulseit module as follows and it works fine now:
module pulseit(clk, reset, pulse);
input clk, reset;
output pulse;
reg [25:0] count;
wire pulse;
always # (posedge clk, posedge reset)
if (reset) count <= 26'b0; else
if (pulse) count <= 26'b0; else
count <= count + 26'b1;
// Let's say pulse goes HIGH when 26th bit of count goes HIGH.
assign pulse = count[25]; // NEED TO DRIVE PULSE
endmodule
I have created a testbench for the above design at EDAPlayground for your reference. Some basic info about Verilog/SV modules can be found at this link and this link.
Note : When assigning, Array index must be in range of index to not overflow.