In Verilog, I can find two system functions to read data from text file. One is $readmemb/$readmemh, other is $fscanf. I am confused between what is difference of the two. Can I simply always use $readmemb and forget about $fscanf?
My understanding is $readmemb is used to initialize memory but that way it can initialize any variable. For example, I have text file with stream of 0s and 1s and I want to read it and store it and then feed them serially into shift register 1 bit every clock.
reg [63:0] seq_input;
$readmemb("pattern.in", seq_input);
I think think this will put streams of zero and one into seq_input at one go and then I can use delay to feed bits from this to DUT.
Why would I use $fscanf and what would be the difference?
The difference between $readmemb/h and $fscanf is how the file is parsed. $fscanf presents the typical C-style interface to a file (mostly) and let's you parse it however you want with format strings. $readmemb/h takes in a file with a very well-defined structure and does all of the parsing for you.
So, you would probably just use $readmemb in your case and forget handling the parsing yourself, but you could use $fscanf for the job if you really wanted to (with more work in general, you have to open the file first at minimum). Remember though that any of these system call needs to be made from a procedural block, like so:
reg [63:0] seq_input;
...
initial begin
$readmemb("my_file.b", seq_input);
end
Where your file looks like this in a text editor:
101001000110011...
If you want more on the $readmemb/h format, Ive answered that question here:
How to initialize contents of inferred Block RAM (BRAM) in Verilog
Related
I've been using Verilog and SystemVerilog for many years, but I just came across something which seems weird.
I don't know if it's something I just never noticed or if there is something special about this I am missing.
Basically I have a module which has a 16-bit input, to which I connected an 8-bit signal. This seems like no big deal to me, in fact it's one of the things I love about Verilog/SystemVerilog, since unlike VHDL, you are allowed to do things like that.
I would expect the signal connected to the input port of my module to be right-aligned and zero-padded on the left, but instead it is being padded with Zs.
That causes my simulation to not work, because for example I use that signal to initialize a counter after substracting one from it, which leads XXXX.
Is this behaviour expected? Can I change something in my code to get the behaviour I expected?
This behavior seems reasonable. I ran a simulation on several simulators on EDA Playground, and I got a mix of results: some had the MSBs as 0, others had them as z.
The best approach is to explicitly drive the inputs with the value you desire. For example, if you want the MSBs to be 0, use something like:
module tb;
reg [7:0] data;
// ...
dut i1 ({ {8{1'b0}}, data });
endmodule
This creates a 16-bit expression which is connected to the module input port. The expression is a concatenation of an 8-bit constant and the 8-bit data signal.
If there is a size mismatch happening in your design or testbench, there should be a warning (if not an error) raised from your compiler/simulation tool. There is no default behavior defined to pad with 0 or undriven z, therefore it can be 0-padded or unknown depending on your tool, and you are on your own risk. The best practice is to watch carefully if there is such warning/error already reported, and try to resolve it during compilation/elaboration phase, or better to run a linting tool before compilation.
Say I have a Verilog module that's parameterizable like the below example:
// Crunches numbers using lots of parallel cores
module number_cruncher
#(parameter NUMBER_OF_PARALLEL_CORES = 4)
(input clock, ..., input [31:0] data, ... etc);
// Math happens here
endmodule
Using Verilog 1364-2005, I want to write a testbench that runs tests on this module with many different values NUMBER_OF_PARALLEL_CORES.
One option that I know will work is to use a generate block to create a bunch of different number_crunchers with different values for NUMBER_OF_PARALLEL_CORES. This isn't very flexible, though - the values need to be chosen at compile time.
Of course, I could also explicitly instantiate a lot of different modules, but that is time consuming and won't work for the sort of "fuzz" testing I want to do.
My questions:
Is there a way to do this by using a plusarg passed in from the command line using $value$plusargs? (I strongly suspect the answer is 'no' for Verilog 1364-2005).
Is there another way to "fuzz" module parameterizations in a testbench, or is using a generate block the only way?
Since $value$plusargs is evaluated at runtime, it can not be used to set parameter values, which must be done at compile-time.
However, if you use generate to instantiate multiple instances of the design with different parameter settings, you might be able to use $value$plusargs to selectively activate or enable one instance at a time. For example, in the testbench, you could use the runtime argument to only drive the inputs of a specific instance.
I would like to generate some combinatorial logic, and I would like to use recursive functions for this (with predefined preprocessor arguments, of course).
Simple example: Factorial function
I have a reg [10:0] number; and I want to have the logic for counting it's factorial, but I want some predefined variable msb to be determine the MSB and have number[msb:0] as a starting number, and go on from there.
And module would receive the number and call fact_func(number) which would calcuate the factorial, but only the shortened one.
Is something like this possible in Verilog? Have functions generate logic?
I'm not totally sure what you're asking, but building logic with recursive function calls is very much possible in Verilog. You'll need to build a parameterized module that includes a generate block instantiating itself with a progressively smaller (or larger) parameter value, until you get to the base case.
Here's an example of it in action. You could easily modify this to generate the Fibonacci sequence.
Keep in mind, however, that generating blocks this way can synthesize very, very large. You will need to ensure the tools you're using are succeeding in optimizing it to a reasonable size.
I need to perform basic operations on strings like concatenation,replacement and comparison in my Verilog simulation. How could it be possible? Is there any built-in support?
Thanks in advance.
There is no string datatype in Verilog however verilog does support string literals and using them as byte vectors. This is the example from the spec:
module string_test;
reg [8*14:1] stringvar;
initial begin
stringvar = "Hello world";
$display ("%s is stored as %h", stringvar,stringvar);
stringvar = {stringvar,"!!!"};
$display ("%s is stored as %h", stringvar,stringvar);
end
endmodule
Since strings use the reg datatype you can use the normal operators to manipulate them, keeping in mind each character uses 8 bits.
5.2.3.1 String operations
The common string operations copy, concatenate, and compare are supported by Verilog HDL operators. Copy
is provided by simple assignment. Concatenation is provided by the
concatenation operator. Comparison is provided by the equality
operators. When manipulating string values in vector regs, the regs
should be at least 8*n bits (where n is the number of ASCII
characters) in order to preserve the 8-bit ASCII code.
You'll have to write some tasks or functions if you need operations like searching.
If you have access to a modern simulator which supports SystemVerilog syntax, there is a string data type. Strings can be concatenated and compared. Refer to the IEEE Std (1800-2009).
sjtaheri,
Reviving a dead thread, but I see this question come up, and there is a newer solution for it.
svlib is a free, open-source library of utility functions for SystemVerilog. It includes file and string manipulation functions, full regular expression search/replace, easy reading and writing of configuration files, access to environment variables and wall-clock time, and much more. This project was presented at DVCon 2014.
http://www.verilab.com/resources/svlib/
I'm new to Verilog, and am having a lot of trouble with it. For example, I want to have an array with eight cells, each of which is 8 bits wide. The following doesn't work:
reg [7:0] transitionTable [0:7];
assign transitionTable[0] = 10;
neither does just doing transitionTable[0] = 10; or transitionTable[0] = 8'h10; Any ideas?
(In case it is not obvious and relevant: I want to make a finite state machine, and specify the state transitions in an array, since that seems easier than a massive case switch.)
When using assign you should declare the array as a wire instead of areg.
Since your goal is to design an FSM, there is no need to store the state values in an array. This is typically done using Verilog parameter's, a state register and a next_state with a case/endcase statement.
The following paper shows a complete example: FSM Fundamentals
If this is targeted towards synthesis:
A little beyond what was answered above, there are standard FSM coding styles that you should adhere to so the tools can perform better optimization. As described in the Cummings paper, one-hot is usually best for FPGA devices and in fact ISE(with default settings) will ignore your encoding and implement whatever it thinks will best utilize the resources on the device. This almost invariably results in a one-hot encoded FSM regardless of the state encoding you chose, provided it recognizes your FSM.
OK, so to answer your question, let's dig a little deeper into Verilog syntax.
First of all, to specify a range of bits, either do [MSB:LSB] or [LSB:MSB]. The standard is MSB:LSB but it is really up to you here, but try to be consistent.
Next, in array instantiation we have:
reg WIDTH reg_name NUMBER;
where WIDTH is the "size" of each element and NUMBER is the number of elements in the array.
So, you first want to do:
reg [7:0] transitionTable [7:0];
Then, to assign particular bytes (8 bits = 1 byte), do:
initial begin
transitionTable[0] = 8'h10;
end
A good book to learn Verilog from is FPGA Prototyping By Verilog Examples by Pong P. Chu.