I need to perform basic operations on strings like concatenation,replacement and comparison in my Verilog simulation. How could it be possible? Is there any built-in support?
Thanks in advance.
There is no string datatype in Verilog however verilog does support string literals and using them as byte vectors. This is the example from the spec:
module string_test;
reg [8*14:1] stringvar;
initial begin
stringvar = "Hello world";
$display ("%s is stored as %h", stringvar,stringvar);
stringvar = {stringvar,"!!!"};
$display ("%s is stored as %h", stringvar,stringvar);
end
endmodule
Since strings use the reg datatype you can use the normal operators to manipulate them, keeping in mind each character uses 8 bits.
5.2.3.1 String operations
The common string operations copy, concatenate, and compare are supported by Verilog HDL operators. Copy
is provided by simple assignment. Concatenation is provided by the
concatenation operator. Comparison is provided by the equality
operators. When manipulating string values in vector regs, the regs
should be at least 8*n bits (where n is the number of ASCII
characters) in order to preserve the 8-bit ASCII code.
You'll have to write some tasks or functions if you need operations like searching.
If you have access to a modern simulator which supports SystemVerilog syntax, there is a string data type. Strings can be concatenated and compared. Refer to the IEEE Std (1800-2009).
sjtaheri,
Reviving a dead thread, but I see this question come up, and there is a newer solution for it.
svlib is a free, open-source library of utility functions for SystemVerilog. It includes file and string manipulation functions, full regular expression search/replace, easy reading and writing of configuration files, access to environment variables and wall-clock time, and much more. This project was presented at DVCon 2014.
http://www.verilab.com/resources/svlib/
Related
I recently came across this answer on stackoverflow.
With Verilog, once you take a part-select, the result is unsigned. Use the $signed system task on the part select to make it signed.
Is this method synthesizable (ie the system task $signed)
If it is not synthesizable, is there a different way to perform arithmetic shift on variables like a <= a>>>2 (this should give the quotient when a is divided by 4).
It certainly is synthesizable. Whether your particular tool supports it is another question.
You can also use a cast in SystemVerilog.
res = signed'(registers[0][0]) >>> 2;
I need to generate random 1023 bit vectors in Verilog. I need something that I can put in the testbench to generate such vectors and feed these vectors to the design under test
As mentioned in the comments, concatenated calls to $random might serve your purpose unless you really need to avoid the 32-bit periodicity (which might still be possible via $random but Im not sure how best to do it if possible).
Better would be to use some SystemVerilog constructs, namely random classes:
class myVector;
rand bit [1022:0] vec; // 1023 bits
endclass
...
myVector vec = new;
vec.randomize();
getRandomVector <= vec.vec;
vec.randomize();
getAnotherRandomVector <= vec.vec;
If you want to ensure no repeats from multiple calls to .randomize(), you can declare vec to be randc instead (you can read more on the exact differences in IEEE 1800-2012 Ch 18). You can also provide constraints on the randomization to only get vectors of a certain form if you need it (like limit the number of 1s or anything like that).
In Verilog, I can find two system functions to read data from text file. One is $readmemb/$readmemh, other is $fscanf. I am confused between what is difference of the two. Can I simply always use $readmemb and forget about $fscanf?
My understanding is $readmemb is used to initialize memory but that way it can initialize any variable. For example, I have text file with stream of 0s and 1s and I want to read it and store it and then feed them serially into shift register 1 bit every clock.
reg [63:0] seq_input;
$readmemb("pattern.in", seq_input);
I think think this will put streams of zero and one into seq_input at one go and then I can use delay to feed bits from this to DUT.
Why would I use $fscanf and what would be the difference?
The difference between $readmemb/h and $fscanf is how the file is parsed. $fscanf presents the typical C-style interface to a file (mostly) and let's you parse it however you want with format strings. $readmemb/h takes in a file with a very well-defined structure and does all of the parsing for you.
So, you would probably just use $readmemb in your case and forget handling the parsing yourself, but you could use $fscanf for the job if you really wanted to (with more work in general, you have to open the file first at minimum). Remember though that any of these system call needs to be made from a procedural block, like so:
reg [63:0] seq_input;
...
initial begin
$readmemb("my_file.b", seq_input);
end
Where your file looks like this in a text editor:
101001000110011...
If you want more on the $readmemb/h format, Ive answered that question here:
How to initialize contents of inferred Block RAM (BRAM) in Verilog
I was trying to write a program using 2-D net array. But when the code is checked it shows an error (expecting ';', found '['). How should I declare a 2d net array and how to use it ?
Below is the simple code for I written for verification (shows the above error).
module bin(a);
input [0:1] a[0:2];
endmodule
Multidimensional arrays and unpacked arrays as ports are not supported in Verilog. The only arrays Verilog supports in port lists are simple packed arrays (aka vectors).
SystemVerilog does support multidimensional arrays in all variations. All modern Verilog simulators are actually SystemVerilog simulators with backward comparability.
The preferred method to differentiate Verilog and SystemVerilog files is with the file extension. SystemVerilog files should use .sv while Verilog uses the the traditional .v.
Alternativly, simulators have an option to force .v files to be compiled as SystemVerilog. Several use -sv as the compiler option but some use a differnt identifier so you will need to refer to your manual or help-file. The disadvantage to this is approach happens when you are mixing legacy verilog files that happen to use variable/net names that became keep words in SystemVerlog. Using the proper file extension mitigates this risk by compiling each file based in the extension name.
You can't have an unpacked array in ports. Please note that Verilog is a Hardware Description Language, not a Software Language. Only those things will be supported in Verilog, which can be mapped into real hardware.
You can have a packed array in port, not an unpacked array.
Packed array, can be thought of as a bunch of wires in simplest terminology. However, unpacked arrays are not stored consecutively and hence they can't be treated as simple bunch of wires.
module bin(a);
input a[2:0][1:0];
endmodule
This should work, since it is a packed array dimension.Or else you can use a bus to represent your inputs and break it.
module bin(a);
input a[5:0];
wire [1:0] a1, a2, a3;
assign {a1,a2,a3} = a;
endmodule
I'm new to Verilog, and am having a lot of trouble with it. For example, I want to have an array with eight cells, each of which is 8 bits wide. The following doesn't work:
reg [7:0] transitionTable [0:7];
assign transitionTable[0] = 10;
neither does just doing transitionTable[0] = 10; or transitionTable[0] = 8'h10; Any ideas?
(In case it is not obvious and relevant: I want to make a finite state machine, and specify the state transitions in an array, since that seems easier than a massive case switch.)
When using assign you should declare the array as a wire instead of areg.
Since your goal is to design an FSM, there is no need to store the state values in an array. This is typically done using Verilog parameter's, a state register and a next_state with a case/endcase statement.
The following paper shows a complete example: FSM Fundamentals
If this is targeted towards synthesis:
A little beyond what was answered above, there are standard FSM coding styles that you should adhere to so the tools can perform better optimization. As described in the Cummings paper, one-hot is usually best for FPGA devices and in fact ISE(with default settings) will ignore your encoding and implement whatever it thinks will best utilize the resources on the device. This almost invariably results in a one-hot encoded FSM regardless of the state encoding you chose, provided it recognizes your FSM.
OK, so to answer your question, let's dig a little deeper into Verilog syntax.
First of all, to specify a range of bits, either do [MSB:LSB] or [LSB:MSB]. The standard is MSB:LSB but it is really up to you here, but try to be consistent.
Next, in array instantiation we have:
reg WIDTH reg_name NUMBER;
where WIDTH is the "size" of each element and NUMBER is the number of elements in the array.
So, you first want to do:
reg [7:0] transitionTable [7:0];
Then, to assign particular bytes (8 bits = 1 byte), do:
initial begin
transitionTable[0] = 8'h10;
end
A good book to learn Verilog from is FPGA Prototyping By Verilog Examples by Pong P. Chu.