I am learning Verilog with Altera's (now Intel) Quartus Prime development s/w and a DE0_Nano Cyclone IV dev board. I have the Charles Roth et al book "Digital Systems Design Using Verilog" which seems very good at the Verilog module level. I have also looked through a number of on line tutorials and I have a project working using a single Verilog file which is fine as far as it goes.
What I am missing and cannot find any guidance on is how to split a project into multiple hierarchical Verilog source files. I only want the hierarchy's top level file with the top level module instantiated in the Quartus project's .bdf file (the top level of the project drawn like a circuit).
Anyone any ideas how to do this? I presume simply including the lower level files in the top level Verilog file (via `include directive) is not the best way to do it. (Although do doubt it would work)
Help appreciated,
John
First, create your subcircuit (either in HDL or as a schematic/BDF file). Once your done, save it, and with the subcircuit file open, select File->Create/Update->Create Symbol Files for Current File.
Then, go to your top-level schematic, and click on the Symbol tool. In addition to the standard list of primitives, you should see a group of "Project" symbols. In there, you should find a block for your subcircuit to include in the top-level module.
Just add the Verilog files to the project: Project -> Add/Remove Files in Project... They will be compiled and instantiated as necessary.
Related
I have a design that has Xilinx FIFO IP. I am trying to verify the design using COCOTB based testbench. How can I include a Xilinx based IP for simulation using COCOTB? The simulation tool that I am using is Icarus.
Any help is much appreciated.
Do you already have Icarus set up so that you can compile your design without cocotb?
If so, take a look at one of the Makefiles under cocotb's examples/*/tests/ directory, copy one of them and fill out the variables so that it fits your design (see https://cocotb.readthedocs.io/en/latest/building.html#make-variables to see what they mean).
Then, make SIM=icarus should already do something useful.
I have a FPGA project and theres a module written with Verilog in it,
I want to use it in an PCB Project, what should I do?
Usually you have to prepare your IP (verilog code) inside a package. In both Quartus and Vivado you have special interfaces to do just so.
See Xapp1168 for Vivado:
https://www.xilinx.com/support/documentation/application_notes/xapp1168-axi-ip-integrator.pdf
And when the synthesis is completed i am getting many files like .fw, .mcs, .prm along with .bit file, and can we dump those other files other than .bit file into FPGA? Which one is more advantageous project mode or non project mode? Coding is done in verilog.
The best explanation is probably found in the Xilinx document UG892 which can be downloaded from their website. Chapter 2 Page 18 gives the details:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug892-vivado-design-flows-overview.pdf
Essentially in project mode you add files which get copied into a new directory structure, set options and setup the synthesis/place&route runs that you need and then Vivado manages the acutal commands run. It's more of a push button flow in the IDE, but can also be scripted (again all the setup is at the front end and then you essentially say 'go' and it works out what it needs to do).
In the non-project flow you get complete control over the compilation process (no copying of files, they're just used from the location you give) and the synthesis process and manage all the settings and the commands that are run yourself. It requires a knowledge of TCL to write the scripts, but there are example flows in the documentation.
We use the non-project flow as it doesn't use an binary project files and is entirely scripted from TCL and Makefiles (which is not integral to the way Vivado works, but makes our life so much easier). While a bit trickier to set up, it gives you more control, allows you to checkpoint the design at any point and it is easier to put into a version control system, so you can track changes in constraints and build options.
I have compiled my benchmark and generated the .hex file.
where to include the .hex file in the verilog files.
all what I have for the verilog files are Top.DefaultVLSIConfig.v and memdessertMemDessert.DeafultVLSIConfig.v inside rocket-chip folder
I don't have vcs simulator in my os, can I take the verilog file and the hex file and do the simulation in another platform?
Haider
Yes, you can use another platform. On any platform you use, you will need a verilog simulator. Rocket Chip includes the verilog harness to use vcs, so if you use another simulator you may need to change the harness.
I would recommend using the C++ emulator Rocket Chip provides.
I don't have vcs simulator in my os
You can run your code using vcs simulator 2014.12 in EDAplayground
this isn't really a verilog question, it's a design dependent question, and partly a tool question.
there must be some memory definition somewhere in the code where you have to put a file reference to your hex file. should be pretty simple to find it.
I'm trying to cheaply and accurately predict all the SystemVerilog dependencies for a build flow. It is ok to over-predict the dependencies and find a few Verilog files that aren't sv dependencies, but I don't want to miss any dependencies.
Do I actually have to parse the Verilog in order to determine all its dependencies? There are tick-include preprocessor macros, but those tick-include don't seem to load all the code currently getting compiled. There is a SYSTEM\_VERILOG\_PATH environment variable. Do I need to parse every SystemVerilog file in that SYSTEM\_VERILOG\_PATH variable in order to determine which modules are defined in which files?
One good way (if this is synthesizable code) is to use your synthesis tool file list (e.g. .qsf for Altera). That tends to be complete, but if it isn't, you can look at the build log for missing files that it found.
From a readily compiled environment it is possible to dump the source files
(e.g. Cadence
-- To list source files used by the snapshot 'worklib.top:snap'
% ncls -source -snapshot worklib.top:snap
)
but if you are starting from scratch I am afraid there is no easy solution. I would go for the pragmatic one: have a config file with all the directories that contain .sv files and then compile everything in it. If your project has a proper file structure, you could also modularize this by supplying config files for every major block.
Hope that helps.
I know Questa has a command line option where it will generate a makefile for you with all the dependencies in it after you have compiled your design. I'm not sure if the other simulators have that.
Another option is to browse and dump your compiled library in your simulator. You probably won't get the actual filenames the modules are compiled from, but it'll be a lot easier to parse all your verilog files for the module names that show up in the compiled library.