I'm trying to create a password system with a baysis2 FPGA and verilog that verifies a password which is entered via keyboard. I need to make sure that my keyboard is working properly, as it seems to be a bit glitchy. I was told that the best way to make sure my keyboard is sending data to the board is by checking to see if ps2d and ps2c are high when I press a button, which makes sense. The problem is that in testing, the two LEDs I bound ps2d and ps2c to are ALWAYS LOGICAL HIGH even when the keyboard is disconnected! Is this some feature of verilog/Xilinx ISE or does my board have a bad port?
The following is my Verilog code.
module wtf(ps2d, ps2c, ps2dout, ps2cout);
input wire ps2d, ps2c;
output wire ps2dout, ps2cout;
assign ps2dout = ps2d;
assign ps2cout = ps2c;
endmodule
With the following constraint file
NET "ps2c" LOC = "B1" | DRIVE = 2 | PULLUP ;
NET "ps2d" LOC = "C3" | DRIVE = 2 | PULLUP ;
NET "ps2cout" LOC = "G1" ;
NET "ps2dout" LOC = "P4" ;
Well, the UCF file enables internal pull-ups on those pins, so reading those as high with nothing connected is exactly what it is supposed to do.
Related
I have an USBhub (D-Link DUB-H7) connected to my laptop with Windows 10. Connected to the hub are 4 identical PEAK dongles to talk to a CANbus. Now, my problem is to programmatically identify these 4 seperate dongles and knowing which one is which. The dongles are fixed in the hub.
To start I downloaded and installed USBDeview to view my devices. In the program I can see my 4 PCAN-USB dongles and I can see that their Instance ID are different. That's good, now I have my identifier. However, once I try to get the ID's with Python things aren't looking good. This is my following test program:
import win32com.client
wmi = win32com.client.GetObject("winmgmts:")
input("Connect the hub")
dongle_list = [(usb.name, usb.DeviceID) for usb in wmi.InstancesOf("Win32_USBHub")]
input("Disconnect the hub")
nod_list = [(usb.name, usb.DeviceID) for usb in wmi.InstancesOf("Win32_USBHub")]
diff = list(set(dongle_list) - set(nod_list))
for d in diff:
print(d)
Running this gives me only 2 new usb devices and the ID's point to the USBhub rather than the dongles connected to the hub. I also tried with wmi.InstancesOf("CIM_USBDevice") but the result stays the same.
('Generic USB Hub', 'USB\\VID_05E3&PID_0608\\5&4A43CD6&0&4')
('Generic USB Hub', 'USB\\VID_05E3&PID_0608\\6&9EBFB9C&0&4')
So how can I retrieve the usb information of the devices connected to the USBhub using Python or powershell/cmd invoked by Python?
Another route I was thinking I could take is by using port identifiers. If I disconnect a dongle I can see that it was connected to Port_#0001.Hub_#000x, where is x is a positive integer. So maybe I could poll the port to see if the dongle is connected and then I too know which one is which (dongles are fixed in the hub). Although I think that using the Instance ID is more foolproof.
I ended up creating a powershell command and invoke that using Python. I noticed however that the InstanceID's are hardware addresses of the the USBhub and not the dongles.
I also noticed that the dongles sometimes switch their addresses related on how they were connected. So I also needed to disable them and enable them again in the order I want.
This is what I have now:
poll_cmd = """
$ret = (Get-PnpDevice | ? {($_.description -like "*pcan*") -and ($_.status -eq "ok")} | sort instanceid).instanceid;
$ret | % {Disable-PnpDevice $_ -Confirm:$False};
$ret | % {Start-Sleep -Seconds 1; Enable-PnpDevice $_ -Confirm:$False};
$ret
"""
usbs = (
subprocess.check_output(["powershell.exe", poll_cmd])
.decode()
.strip()
.split("\r\n")
)
usbs holds the list of usb dongles I'm interested in.
However this gave me one more problem: UAC. I need admin rights to enable the usbs. And used the top answer from Request UAC elevation from within a Python script? to give my program admin rights.
I am working on project in which I have to read 5 bits binary values from text file. I have to read each 5 bit binary number and then assign them to 5 different 1 bit registers one by one. Moreover i can't use 'memreadb' because my text file is so huge almost 2mb and I think 'memreadb' can't deal with such a huge file because its not working in my case. so can anyone please tell me how to use 'fopen' and 'fread' function to solve my problem because i have not work on file handling in Verilog till now. And can anyone provide me an example similar to my problem?
Thanks,
Sami
You can use $fscanf to read your file one line at a time.
integer status, fd;
reg [4:0] value;
initial begin
fd = $fopen("data_file.dat", "r");
if (!fd) $error("could not read file");
while (!$feof(fd)) begin
status = $fscanf(fd,"%b",value);
// check status, then do what you need to do with value
end
end
I'm trying to write a top-level module in Verilog that will open a water valve whenever a sensor reads values below a certain number.
Here is my code:
module ProjectDSD(alteraClock, sensorInput, openValve);
input sensorInput, alteraClock;
output openValve;
always #(sensorInput)
begin
if(sensorInput < 100) //sensor value to irrigate at
begin
openValve <= 1; //here
end
else
begin
openValve <= 0; //here
end
end
endmodule
Im getting an error saying:
Object "openValve" on left-hand side of assignment must have a variable data type
What am I missing? Also, which pins can I use on an Altera DE2-155 board to output a digital signal of only 1's and 0's for the the valve to open/close?
s/output openValve/output reg openValve/
Outputs default to wire; you need a reg. See also this question.
openValve is currently inferred as a wire. Add reg openValve; below output openValve; and your code will work.
Suggestions: It looks like you are following the IEEE1364-1995 non-ANSI coding style. Will still legal, you might want to change to the ANSI coding style, supported in IEEE1364-2001 and above.
Non-ANSI:
module ProjectDSD(alteraClock, sensorInput, openValve);
input sensorInput, alteraClock;
output openValve;
reg openValve;
ANSI:
module ProjectDSD(
input alteraClock, sensorInput,
output reg openValve);
For combinational blocks, it is recommended to use always #* (or the synonymous always #(*)) instead of always #(sensorInput). #* is an auto sensitivity list also added in IEEE1364-2001
Try output reg openValve;.
For the second half of your question (which should really be a separate question) import this QSF file into your project. Any of the GPIO can be configured as outputs, and are accessible by the 40-pin header on the side.
I have created two different Verilog Modules (shiftByImm and immShifter). What I want to do is to select only the output of one of the two as the output of this little multiplexer module I am creating.
module superShifter(input [0:31] in, input select, input [0:4] shift_value, input[0:1] shift, output reg [0:31] out);
shiftByImm shift0(in, shift_value, shift, out);
immShifter shift1(in, shift_value, out);
assign {out} = select == 1'b0 ? shift0 : shift1;
endmodule
However, this gives me two perfectly understandable errors:
Illegal reference to interface "shift0"andIllegal reference to interface "shift1"
I know that there is something missing here. How do I select the output of the SuperShifter module to be the same output of one of the pre-made modules?
You're issue is with your naming conventions. You have 2 modules (I'm guessing) with 2 different outputs, but you give them the same name. In this example, you are using the port order method. The names in the parentheses are associated implicitly by order and do not need to be the same as what they are inside the instantiation. The other way is to connect the ports by name. In the example I show both methods. From that point, you would have to use the wires declared to choose an output with your "little mux".
module superShifter(input [0:31] in, input select, input [0:4] shift_value, input[0:1] shift, output reg [0:31] out);
wire [0:31] temp_out_0;
wire [0:31] temp_out_1;
shiftByImm shift0(in, shift_value, shift, temp_out_0);
immShifter shift1(.in(in), .shift_value(shift_value), .out(temp_out_1));
assign {out} = select == 1'b0 ? temp_out_0 : temp_out_1;
endmodule
Following on from #N8TROs answer it looks like you are trying to 'call' the modules and have them generate the output.
Modules are not equivalent to tasks which are called when required they represent physical blocks of hardware. The mux needs to select the output which you want not the module you wish to be active.
As you have both modules driving the same output you will likely see xs When one module drives 1 and the other 0 the wire or net will end up in conflict.
I really agree with N8TROs recommendation to use ANSI style named ports, this really helkps debugging and code maintenance.
but for brevity and to see minimal changes in the code to make it work:
shiftByImm shift0(in, shift_value, shift, out0); //<-- Unique output
immShifter shift1(in, shift_value, out1); //<-- Unique output
assign {out} = select == 1'b0 ? out0: out1; //<-- select output
Under Perl, opening Serial::Device on Linux as a file resets my Arduino, but I don't want it being reset. Arduino can be reset by pulsing DTR, therefore opening the serial device must be pulsing DTR by default.
My question is: How can I prevent my Arduino from being reset (DTR being pulsed)?
This minimal code resets my Arduino:
use Device::SerialPort;
use Symbol qw( gensym );
my $handle = gensym();
my $PortName = '/dev/ttyUSB1';
my $PortObj = tie( *$handle , "Device::SerialPort" , $PortName ) or die "Cannot open serial port: $!\n";
# At this point the Arduino is being reset.
I know it is simply done by opening the device with PortObj = new Device::SerialPort ($PortName, $quiet, $lockfile); method, but I can't use that method because I'm unable to check if there is data waiting in the serial buffer. And testing for data waiting is a hard requirement in my program.
You need to change the HUPCL bit in the termios setting for the port. This will persist until something else changes it (I've seen different versions of the same distro default it differently)
See man termios and man stty
The following shell command might work - untested:
stty -F /dev/ttyUSB1 -hupcl