Verilog (register delay or mistake in code?) - verilog

Question

I am trying to study Verilog
and I got problem with my code:
the problem is when I trying to add my numbers like
first value clk> second value clk> 3rd value clk> 4th value clk>and here supposed to be my average value BUT for some unknown reason I need to press clock 2 times AGAIN to get averege value
and I don't know why. (I think there is a problem in my code with avereger)
why I have such delay
my avereger must get 4 - 10 bits numbers and show me the averege of it (on my leds)
Here is my code
and I am including my vector form [
]
module avereger (data_in,Led1,Led2,Led3,clk,rst);
input clk,rst;
input [9:0]data_in;
output[6:0] Led1,Led2,Led3;
reg [9:0] data[3:0];
reg [11:0] sum,avg_reg;
always # (posedge clk)
begin
if(rst==1'b1)
begin //all values will be 0
data[0]<=0;
data[1]<=0;
data[2]<=0;
data[3]<=0;
sum<=0;
avg_reg<=0;
end
else
begin
data[3]<=data[2];
data[2]<=data[1];
data[1]<=data[0];
data[0]<=data_in;
sum<= data[0] + data[1] + data[2] + data[3];
avg_reg<=sum[11:2];
end
end
decoder_driver BCD(avg_reg,Led1,Led2,Led3);
endmodule
module decoder_driver(A,Led1,Led2,Led3);
input [9:0] A;
output [6:0] Led1,Led2,Led3;
reg [3:0] B,C,D;
wire [3:0] wireB,wireC,wireD;
assign wireB=B;
assign wireC=C;
assign wireD=D;
display1 HUN(wireB,Led1);
display1 TEN(wireC,Led2);
display1 ONE(wireD,Led3);
always # (A)
begin
B=A/7'd100;
C=A%7'd100/7'd10;
D=A%7'd100%7'd10;
end
endmodule
module display1 (a,Led);
input [3:0] a;
output [6:0] Led;
reg [6:0] Led;
always # (a)
begin
case(a)
4'b0000: Led <= 7'b1000000; //0
4'b0001: Led <= 7'b1111001; //1
4'b0010: Led <= 7'b0100100; //2
4'b0011: Led <= 7'b0110000; //3
4'b0100: Led <= 7'b0011001; //4
4'b0101: Led <= 7'b0010010; //5
4'b0110: Led <= 7'b0000010; //6
4'b0111: Led <= 7'b1111000; //7
4'b1000: Led <= 7'b0000000; //8
4'b1001: Led <= 7'b0010000; //9
4'b1010: Led <= 7'b0001110; //F
default: Led <= 7'b1111111; //-
endcase
end
endmodule

Answer 1

The reason the code is taking 6 total cycles instead of 4 is because calculating sum and avg_reg takes a cycle each, thus combined with the 4 cycles needed to shift in the 4 data items, and you get 6 cycles.
If you watch what happens during simulation, you'll notice shifting in the 4 items takes 4 cycles as expected. However, sum is, at the edge the 4th value is take into data[0], the sum of the first third items and whatever was in data[4] which is probably all zeroes if you've just done a reset. And avg_reg is the value of sum from right before the edge shifted over twice. On the next cycle sum becomes correct and then the cycle after that avg_reg becomes correct.
If you want to remove these cycles, you can simply have sum determined combinationally and don't really need avg_reg at all:
module avereger (data_in,Led1,Led2,Led3,clk,rst);
input clk, rst;
input [9:0] data_in;
output[6:0] Led1,Led2,Led3;
reg [9:0] data[3:0];
wire [11:0] sum;
always # (posedge clk) begin
if(rst==1'b1) begin //all values will be 0
data[0]<='0;
data[1]<='0;
data[2]<='0;
data[3]<='0;
end
else begin
data[3]<=data[2];
data[2]<=data[1];
data[1]<=data[0];
data[0]<=data_in;
end
end
// Find sum combinationally
assign sum = data[0] + data[1] + data[2] + data[3];
// Do >>2 here
decoder_driver BCD(.A(sum[11:2]),
.Led1(Led1),
.Led2(Led2),
.Led3(Led3));
endmodule
Side note, you should avoid writing your own sensitivity lists as its very easy to make mistakes, use always #(*) instead of always #(A) in your other modules.