As I said, seedValue wire is holding a 10 bit partial seed which I want to assign to a register when the rst signal is 1 it enters the block and the last statement of this block assigns the seedValue wire to the register temp so that when the if condition if((temp!=10'b0000000000) || (temp!=10'bxxxxxxxxxx)) is executed it enters the block and then the seedValue is concatenated with 12'b000000000000 and then I get my 32-bit seed value through which I am expecting to have random patterns from the LFSR after that the register temp is assigned zero values so that the else block must execute from which I am expection to get random patterns, but the following code is not working. I am new to Verilog and FPGA world, somebody please help me. The following code is written in Verilog.
module TestPatternGenerator(input wire clk, input wire rst, input wire enable,
input wire sel, input wire[9:0] seedValue, output reg[127:0] valueO);
integer i;
reg [31:0] patternGenerate[0:3],tempOne;
reg [9:0] temp;
always #(posedge clk)begin
if((sel == 1)&&(enable==1))begin
if(rst)begin
valueO = 128'b0;
patternGenerate[0]<=32'b0;
patternGenerate[1]<=32'b0;
patternGenerate[2]<=32'b0;
patternGenerate[3]<=32'b0;
tempOne <= 32'b11111111111111111111111111111111;
temp <= seedValue;
end
else if((temp!=10'b0000000000) || (temp!=10'bxxxxxxxxxx))begin
tempOne <= {12'b000000000000,seedValue};
$display("%h",tempOne);
temp <= 10'b0000000000;
end
else begin
for(i=0;i<4;i=i+1)begin
tempOne = {(tempOne[31] ^ tempOne[25] ^ tempOne[22] ^ tempOne[21] ^ tempOne[15] ^ tempOne[11] ^ tempOne[10] ^ tempOne[9] ^ tempOne[7] ^ tempOne[6] ^ tempOne[4] ^ tempOne[3] ^ tempOne[1] ^ tempOne[0]), tempOne[31:1]};
patternGenerate[i] = tempOne;
end
valueO = {patternGenerate[3],patternGenerate[2],patternGenerate[1],patternGenerate[0]};
end
end
i=i+1;
end
endmodule
code for testbench is given below
`timescale 10ns/1ns
module test_controller();
integer j;
reg [127:0] key_byte,valueI,oraI;
wire [127:0] state_byte;
wire [9:0] seedValue;
wire [47:0] result;
reg [7:0] iterate;
reg clk,rst,bistForDeternimistic,deterministicEnable,ecryptionEnable,enable,decryptionEnable,decryptionSecondEnable,bistMode,bistForEncryption,bistForDecryption,oraEnable;
wire [127:0] state_out_dec,state_out_enc,state_second_dec;
wire [31:0] state_out_ora;
reg [31:0] signatureToMatch;
wire load,ready;
TestPatternGenerator tpg (clk,rst,enable,bistMode,seedValue,state_byte);
always #3 clk = ~clk;
initial begin
bistMode <= 1;
key_byte <= 128'h5468617473206D79204B756E67204675;
bistForDecryption <= 0;
clk<=0;
rst<=1;
#5 rst<=0;
iterate<=0;
j<=0;
bistForDeternimistic<=1;
enable<=1;
end
always#(negedge clk)begin : deterministic_block
if(j==100)begin
disable deterministic_block;
end
if((bistMode==1) && (bistForDeternimistic==1))begin
#(state_byte)begin
$display("%h %d",state_byte,$time);
end
end
j=j+1;
end
endmodule
output i am getting only the first test pattern but it should generate 100 test patterns. So except the first test pattern, i am not getting the rest 99 patterns.
When I run your code, I don't see any patterns (the $display statements are not executed). This is because the enable signal is unknown when rst is 1.
If I delay the rst rising edge to occur after enable is set to 1, I see 100 patterns:
initial begin
bistMode <= 1;
key_byte <= 128'h5468617473206D79204B756E67204675;
bistForDecryption <= 0;
clk<=0;
rst<=1;
iterate<=0;
j<=0;
bistForDeternimistic<=1;
enable<=1;
#5 rst<=0;
end
This is a partial output:
00000000000000000000000000000000 3
afffffff5fffffffbfffffff7fffffff 9
2affffff55ffffffabffffff57ffffff 15
72afffffe55fffffcabfffff957fffff 21
272affff4e55ffff9cabffff3957ffff 27
4272afff84e55fff09cabfff13957fff 33
You mention the seedValue signal in your question, but it is undriven (the value z). You declared the signal as a wire, and wires default to z when they are not assigned.
To drive it with a know value for the full duration of the simulation, you could use, for example:
wire [9:0] seedValue = 1;
If you want to drive it like your other inputs, you should declare is as a reg.
I'm totally new to Verilog programming and I do not understand where to initialize reg variables?
Let's have a look at the following snippets:
Edit:
Warning at synthesize
module test (
output LED0
);
reg led = 1'b1;
assign LED0 = led;
endmodule
or
module test (
output LED0
);
reg led;
initial begin
reg led <= 1'b1;
end
assign LED0 = led;
endmodule
Give me: Using initial value of led since it is never assigned at the line: reg led = 1'b1;
Are reg types only assigned in always# block?
Another example:
module fourBitCounter
(input clk,
output [3:0]counter
);
wire clk;
initial begin
reg[3:0] counter = 4'b1;
end
always# (posedge clk) begin
if(counter > 15)
counter <= 0;
else
counter <= counter + 1;
end endmodule
Here the reg has an initial value of 0 but I've set it before to 1... What's wrong? Thank you!
Are reg types only assigned in always# block?
No, reg types can be assigned in always blocks and initial blocks (plus task and function but I'll skip them in the scope of this question)
For your fourBitCounter, the reg[3:0] counter declared in the initial block creates a local variable also called counter that is only accessible within the scope of the block it was created in. You need to remove the reg[3:0] in the initial block so that the assignment get applied the the intended counter. But it will still not work because you declared counter as an inferred wire type and always/initial blocks cannot assign wires.
counter was declared as an output of a 4-bit inferred wire (output [3:0] counter is synonyms to output wire [3:0] counter). Since counter is assigned in an always block and initial block it needs to be a reg type. Therefore it should be declared as output reg [3:0] counter.
Also, you declared clk as in input and as a local wire, it cannot be both. Ports can be accessed locally, there is no reason to re-declare them as local nets.
FYI: for a 4-bit value, 15+1 equals 0 because there is nothing to store the MSB.
module fourBitCounter (
input clk,
output reg [3:0] counter // 'output reg', not 'output'
);
//wire clk; // do not do this, clk is an input
initial begin
counter = 4'b1; // no 'reg' here
end
always #(posedge clk) begin
if(counter > 15) // this will never evaluate as true with counter declared as 4-bit
counter <= 0;
else
counter <= counter + 1;
end
endmodule
For Verilog, assign statements can only be applied on net types (e.g. wire). This is legal:
module test ( output LED0 ); // LED0 is an inferred wire
assign LED0 = 1'b1;
endmodule
This is illegal:
module test ( output reg LED0 ); // Explicit reg
assign LED0 = 1'b1; // illegal, assign on a reg
endmodule
From your first code sample:
reg led; // <-- This declares one register called "led"
initial begin
reg led <= 1'b1; // <-- This declares a *separate* register called "led"
end // which is only valid in the initial block
The same issue exists in your second sample; you're declaring a separate register in the initial block. Don't use the keywords reg or wire if you're just trying to assign a value.
I'm trying to add a mif file in the Test benh and I am getting ERROR's
here i am using the modelsim simulator and i am getting error as
UNRESOLVED REFERENCE TO MEMEORY
Illegal output or inout port connection for port 'dout'.
Error loading design
`timescale 1ns / 1ps
module ESC_tb;
// Internal TB Signal Definition
reg clock;
reg reset;
wire [4:0] pc_out;
wire [7:0] acc_out;
wire [7:0] mdr_out;
// DUT Instantiation
ESC instESC(.clock (clock),
.reset (reset),
.pc_out (pc_out),
.acc_out(acc_out),
.mdr_out(mdr_out)
);
// Initialize block for Clock and Reset
initial
begin : RESET
reset = 0;
#7 reset = 1;
#18 reset = 0;
end
initial
begin : CLOCK
clock = 1;
#5 clock = 0;
forever #(5) clock = ~clock;
end
// Loading Program and Data Memory
initial
begin : MEMLOAD
#5;
**// GETTING ERROR AT THIS POINT**
$readmemh("program.mif", memory);
/66/
$display("Loaded Memory with program.mif file");
end
initial
begin : DUMP_FINISH
$dumpvars;
#1000
$finish(2);
end
endmodule
MEMORY.FILE
module memory (clock, addr, din, we, dout,clear);
// Input/Output Declaration
input clock;
input [4:0] addr;
input [7:0] din;
input we,clear;
output [7:0] dout;
// Signal Type Definition
wire clock;
wire [4:0] addr;
wire [7:0] din;
wire we;
wire [7:0] dout;// Memory Array Declaration of Size 16x256
reg [7:0] mem [0:31];
// Memory Write Operation
always #(posedge clock)
begin
if(we)
mem[addr] <= din;
if(clear)
mem[addr] <= 0;
end
// Memory Read Operation
assign dout = mem[addr];
// End of Module Declaration
endmodule
memory is a module, $readmemh is looking for an array. You need to give the full path from the test bench to mem (within the memory module), or call $readmemh within the memory module.
From TB: $readmemh("program.mif", ESC_tb.instESC./*rest of path*/.mem);
From memory module: initial $readmemh("program.mif", mem);
I am designing a shift register using hierarchical structural Verilog. I have designed a D flip flop and an 8 to 1 mux that uses 3 select inputs. I am trying to put them together to get the full shift register, but my output only gives "XXXX" regardless of the select inputs.
Flip Flop Code
module D_Flip_Flop(
input D,
input clk,
output Q, Q_bar
);
wire a,b,c,d;
nand(a,D,b);
nand(b,a,clk,d);
nand(c,a,d);
nand(d,c,clk);
nand(Q,d,Q_bar);
nand(Q_bar,b,Q);
endmodule
8 to 1 Mux
module Mux8to1(
input [2:0]S,
input A,B,C,D,E,F,G,H,
output Out
);
wire a,b,c,d,e,f,g,h;
and(a, A,~S[2],~S[1],~S[0]);
and(b, B,~S[2],~S[1],S[0]);
and(c, C,~S[2],S[1],~S[0]);
and(d, D,~S[2],S[1],S[0]);
and(e, E,S[2],~S[1],~S[0]);
and(f, F,S[2],~S[1],S[0]);
and(g, G,S[2],S[1],~S[0]);
and(h, H,S[2],S[1],S[0]);
or(Out, a,b,c,d,e,f,g,h);
endmodule
Hierarchical Combination of the Two
module shiftRegister_struct(
input clk,
input [2:0]S,
input [3:0]L,
output reg [3:0]V
);
wire a,b,c,d;
wire V_bar[3:0];
Mux8to1 stage3(S[2:0],V[3],V[0],V[2],1'b0,V[2],V[3],V[2],L[3],a);
Mux8to1 stage2(S[2:0],V[2],V[3],V[1],V[3],V[1],V[3],V[1],L[2],b);
Mux8to1 stage1(S[2:0],V[1],V[2],V[0],V[2],V[1],V[2],V[1],L[1],c);
Mux8to1 stage0(S[2:0],V[0],V[1],V[3],V[1],1'b0,V[1],1'b0,L[0],d);
D_Flip_Flop stage3b(a,clk,V[3],V_bar[3]);
D_Flip_Flop stage2b(b,clk,V[2],V_bar[2]);
D_Flip_Flop stage1b(c,clk,V[1],V_bar[1]);
D_Flip_Flop stage0b(d,clk,V[0],V_bar[0]);
end module
Any thoughts on what might be screwing up my output? The output is V[3:0].
I should also include my test bench code:
module Shift_Test_Bench;
// Inputs
reg [2:0] S;
reg [3:0] L;
reg clk;
integer i;
integer j;
// Outputs
wire [3:0] V;
// Instantiate the Unit Under Test (UUT)
shiftRegister_struct uut (
.clk(clk),
.S(S),
.L(L),
.V(V)
);
initial begin
// Initialize Inputs
S = 7;
L = 3;
clk = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for(i = 0; i < 16; i = i+1)
begin
S = i;
for(j = 0; j < 2; j = j+1)
begin
clk = !clk;
#5;
end
end
end
endmodule
You have a wiring bug in your D_Flip_Flop module. When I simulated your testbench, I got compiler warnings:
Implicit wire 'f' does not have any driver, please make sure this is
intended.
Implicit wire 'e' does not have any driver, please make sure this is
intended.
Here are the lines:
nand(Q,d,f);
nand(Q_bar,b,e);
Your missing a reset condition, either synchronous or asynchronous. Your flops have an unknown value and never reach known state because the data input is dependent on the flop output. By adding a reset to can put the flops into a known state independent of its outputs (V/V_bar).
In this case adding a synchronous is be easier. Simply add some 2-to-1 muxes and a new reset pin.
Mux2to1 syncrst3(a_d,a,1'b0,reset);
// ...
D_Flip_Flop stage3b(a_d,clk,V[3],V_bar[3]);
// ...
I'm working on a simple sign-extender in Verilog for a processor I'm creating for Computer Architecture.
Here's what I've got so far: [EDIT: Changed the selection statement slightly]
`timescale 1ns / 1ps
module SignExtender( CLK, extend, extended );
input[7:0] extend;
input CLK;
output[15:0] extended;
reg[15:0] extended;
wire[7:0] extend;
always
begin
while (CLK == 1)
extended[7:0] = extend[7:0];
extended[15:8] = {8{extend[7]}};
end
endmodule
I added the while (CLK == 1) thinking that would solve my problem, which I believe is an infinite loop. When I try to test this in iSim, the circuit never initializes.
I also tried removing the copying syntax and just doing extended[8] = extend[7] etc. for [8]-[15], but the same result occurs, so I'm pretty sure that the innermost syntax is correct.
Here's the test file:
`timescale 1ns / 1ps
module SignExtender_testbench0;
// Inputs
reg [7:0] extend;
reg CLK;
// Outputs
wire [15:0] extended;
// Instantiate the Unit Under Test (UUT)
SignExtender uut (
.extend(extend),
.extended(extended)
);
initial begin
// Initialize Inputs
extend = 0;
#100; // Wait 100 ns for global reset to finish
extend = -30;
CLK = 1;
#10;
CLK = 0;
if (extended == -30)
$display("okay 1");
else
$display("fail 1");
extend = 40;
#10;
if (extended == 40)
$display("okay 2");
else
$display("fail 2");
end
endmodule
Any ideas how I can do this successfully?
You nearly got it...
always #( posedge clk ) begin
extended[15:0] <= { {8{extend[7]}}, extend[7:0] };
end
You're also missing a clock edge for the '40' test. Try this, & let me know how you get on...
We can use the syntax $signed to sign extend
module signextender(
input [7:0] unextended,//the msb bit is the sign bit
input clk,
output reg [15:0] extended
);
always#(posedge clk)
begin
extended <= $signed(unextended);
end
endmodule
By the way your module assign is pure combinational so it should not contain a clk, this is another way of doing your module:
module sign_ext
(
unextend,
extended
);
input [15:0] unextend;
output [31:0] extended;
assign extended = {{16{unextend[15]}}, unextend};
endmodule
//TB
module tb_sign_ext;
reg [15:0] unex;
wire [31:0] ext;
sign_ext TBSIGNEXT
(
.unextend(unex),
.extended(ext)
);
initial
begin
unex = 16'd0;
end
initial
begin
#10 unex = 16'b0000_0000_1111_1111;
#20 unex = 16'b1000_0000_1111_1111;
end
endmodule
;)