According to the riscv-gcc compiler we are generated the binary file. This binary file data are feeding to rocket chip through this signals.
io_host_in_valid, input [15:0] io_host_in_bits
Here io_host_in_bits is 16-bit, so we are driving the 2-times for each instruction data in little-Endian mode.
We are not getting any response from Rocket core (HTIF).
How to simulate the Rocket core and if it is possible to simulate in Xilinx Vivado 2014 as well as debug the design.
Can any one help me about this
Regards,
Santhosh Kumar.
For more information on the Rocket Chip infrastructure, I recommend checking out the slides and videos from the first RISC-V Bootcamp.
The Rocket Chip can be simulated/debugged in two different ways: C simulator and Verilog. For information on using these modes, please consult the Rocket Chip README.
Yunsup's response on the riscv-hw mailing list:
I would take a look at http://riscv.org/tutorial-hpca2015/riscv-rocket-chip-generator-tutorial-hpca2015.pdf for an overview of interfaces and the FPGA setup.
Here’s a link to our test bench we use to test the rocket chip: https://github.com/ucb-bar/rocket-chip/blob/master/vsrc/rocketTestHarness.v. I would take a look at the htif_tick function, where the implementation can be found here at https://github.com/ucb-bar/rocket-chip/blob/master/csrc/vcs_main.cc, which calls a method on htif_emulator_t (https://github.com/ucb-bar/rocket-chip/blob/master/csrc/htif_emulator.h), which is inherited from htif_pthread_t (https://github.com/riscv/riscv-fesvr/blob/master/fesvr/htif_pthread.cc). You should also take a look at https://github.com/riscv/riscv-fesvr/blob/master/fesvr/htif.cc.
The host interface (HostIO) doesn’t take instructions directly, it’s a port for the front-end server (https://github.com/riscv/riscv-fesvr/tree/master/fesvr) to access target memory and the core’s control and status registers (CSR).
Related
I work with Zedboard and vivado v2017.3.
I have a custom IP in the PL part of zynq generating 32 bit values and stores them in one of the registers, say slv_reg0 (address : 0x43c00000).
In the PS part I read this register and I can print it in the gtkterm (simple one).
I now want to transmit these values over ethernet to to the PC.
Any suggestion on how to carry out this?
Thanks,
Upasana.
Xilinx supplies sample programs, one of these is an echo server. It should be quite simple to change it so that it serves the data you generate instead of just echo-ing the received message, and you can learn out of it how to use the lwip library in case you want a more suitable solution.
I've to design an IO-module for an industrial control system in a CAN-bus network.
The IO-pins (10-40 pins) have to be all multi purpose: digital and analog in- and output. Further the pins have to serve as a communication port when needed: Modbus RTU, modbus TCP, DALI, etc. (Analog input max 7 channels)
I understand that all of this options need different HW; like galvanic isolation or different voltage levels etc.
Costs have to be as low as possible.
I was thinking of making this bit of additional hardware as a plug-in module or as an optional additional sandwich PCB.
My question is: Is an FPGA the right choice for this because of the reconfigurable purpose of the IO-pins? (Xilinx, altera/intel and microsemi have FPGA's with ADC's)
You didn't specify if IOs have to be reconfigurable at compile or runtime. In most cases, you cannot change IO properties (type, voltage, terminations,etc.) once HDL code is compiled into FPGA bitstream.
I am attempting to use the IP packaging tools in Xilinx Vivado to create a co-processor with an AXI-Lite interface and utilize it in a Zynq SoC design for my Digital Systems Engineering class. The co-processor is a GCD calculator that we have already developed as part of a previous assignment. I followed the instructor's directions to create an IP out of the GCD calculator, and we loosely followed Tutorial 4A from the PDF located here to create the AXI interface (the I/O declarations are obviously modified to accomodate the GCD calculator). I have a data bus called 'data' running from the AXI IP and the GCD IP to send values to the calculator. However, when I attempt to Synthesize the design, I get an the following error:
[Synth 8-685] variable 'data' should not be used in output port connection'
The error directs to the line of my AXI bus interface instantiation where my data port is defined.
I've been searching online for a solution to this error for hours, but not even the Xilinx website, nor the Xilinx documents that have been made available to us, have any information regarding this error, and I have not been able to find any accounts from anyone experiencing the same error.
I emailed the professor to see if he has any ideas, but he probably won't be awake for another six hours and the assignment is due today (tomorrow?).
Has anyone heard of this error, or have any idea of how to correct it?
Here's a portion of code that contains the error's source:
// Instantiation of Axi Buss Interface S00_AXI
myip_v1.0_0_S00_AVI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) myip_v1_0_S00_AXI_inst (
.done_async(done_async),
.go(go),
.data(data), // The error points to this line
.S_AXI_ACLK(s00_axi_aclk),
... // all remaining ports were generated by the IP tools
);
Thanks,
-Andrew
It looks to me like you are trying to drive a variable from the output of an instantiated module. In Verilog you cannot drive a variable from an instantiated module. This is illegal in Verilog (though it is not in SystemVerilog):
reg OP; -- this is a variable
SOME_MODULE MODULE_INST (.IP(IP), .OP(OP));
whereas this is not illegal:
wire OP; -- this is a net
SOME_MODULE MODULE_INST (.IP(IP), .OP(OP));
I am trying to write a verilog code for FPGA which will output sound from the embedded "line out" pin. I use Quartus II and Altera DE1.
I am new to hardware programming, therefore it just takes too much time for me to catch up with basics. Apparently I need to initialize the wolfson chip and need to write something to communicate with it, as discussed here:
http://www.alteraforum.com/forum/showthread.php?t=6005
It uses wolfson WM8731 codec, manual is in here:
http://www.rockbox.org/wiki/pub/Main/DataSheets/WM8731_8731L.pdf
and an example I found but couldnt figured out how to use it is in here:
https://code.google.com/p/vector06cc/wiki/SoundCodec
I have found bunch of examples about how to generate sounds using GPIO pins, but barely anything about the usage of WM8731. I would really appreciate any guidance or experience you might share.
Assuming you're using Nios II and either SOPC Builder or Qsys, the Altera University Program offers an IP core to control the Audio CODEC on the DE-Series boards.
If you don't already have it, you can download it here (at the bottom of the page, listed as University Program Installer): https://www.altera.com/support/training/university/materials-ip-cores.html
Once you install it, check the <altera-directory>/University_Program\NiosII_Computer_Systems\DE1\DE1_Media_Computer directory. app_software and app_software_HAL both give example methods to write to the audio output (using C code running on the Nios II), and the verilog or vhdl folder show example systems on connecting the core to a NIOS II using your preferred HDL.
The core itself can be found in <altera-directory>\ip\University_Program\Audio_Video. See also ftp://ftp.altera.com/up/pub/Altera_Material/14.1/University_Program_IP_Cores/Audio_Video/Audio.pdf for some (potentially) helpful reading/reference.
Addendum:
All of the FPGA inputs and outputs use the "Digital Audio Interface" of the WM8731 chip. The pins available on the FPGA are as follows:
PIN_A6 : AUD_ADCLRCK
PIN_B6 : AUD_ADCDAT
PIN_A5 : AUD_DACLRCK
PIN_B5 : AUD_DACDAT
PIN_A4 : AUD_BCLK
PIN_B4 : AUD_XCK (MCLK on WM8731)
Output is sent to the CODEC on the AUD_DACDAT pin.
The chip is configured using the I2C_SDAT and I2C_SCLK pins on I2C address 0x34 for read, and 0x35 for write.
No other pins are available to the FPGA - some are used for external connections (like the mike or line-in), or are not connected at all.
For a full list of pin assignments for the DE1 (which can be directly imported to Quartus) see: ftp://ftp.altera.com/up/pub/Altera_Material/12.1/Boards/DE1/DE1.qsf
How can I configure one pin for input and another for the output?
If I am not wrong this could be done with GPIO registers that controlls device pins that are not connected to peripherical functions.
Look in UM10360.PDF, Chapter 9: GPIO. There you can find the description for the FIOxDIR direction registers, as well as the reigisters for querying, setting and clearing GPIO pins.
I also strongly recommend looking at the CMSIS Standard Peripherial Driver Library that NXP offers for 175x/176x, look in microcontroller support documents. Edit: There are lots of sample code in this Library.
https://github.com/dwelch67
I have a number of lpc based examples. You are looking for the IODIR register, depending on the port and flavor of LPC, there are now what they call fast I/O registers. a one in a bit location means that pin is an output, a zero an input.