I am trying to create a circuit in Logisim that can count upwards using the 7-segment display as the output. It needs to run using a clock, and automatically count from 0 to 9 and then back to 0 again, in a continuous loop. I don't know where to start on this and I was wondering if anyone has any tips? Thanks in advance.
Use ROM, along with a binary to BCD converter. Look up the double dabble algorithm- useful for your purpose.
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I am very new to python and programming in general so I am hoping someone might be able to point me in the right direction in my search for a solution;
In controlling a linear actuator, I need to be sure the speed is constant over varying loads.
The motor controller receives byte values of 0(stopped)-127(full speed) over serial to control speed
The position is a voltage from 0-5v with 5v being fully retracted and 0v being fully extended.
I have looked up simple - PID but Im not sure I understand how I would apply it in this case.
Essentially I would specify every 0.x seconds, check the position relative to the previous position, calculate the speed, and then update the speed value being sent over the serial port so I reach my speed setpoint.
If someone could detail what should go where, specifically what the tunings are for?
https://pypi.org/project/simple-pid/
Thanks!
I tried to run the code below, but it doesn't let me select the same DAQ channel for both readings, despite the fact they should be taken from the same DAQ channel/encoder. Any suggestions would be welcome.
You can use the same input terminal to perform both measurements, but you cannot use the same counter to do so. I cannot see the values for your Counter(s) IO Controls, but I suspect they are requesting the driver use the same counter to do two different things.
Try using two counters like this instead. See how PFI8 is used as the input terminal for both tasks:
I was searching a lot about this problem, but I cant find anything usefull...
The problem is, Im making echo efect on FPGA chip.. I have everything prepared, like BRAM for delay, input, output with delay, but I can't find out, how to change volume of output which is coming back to input, to mix them together and send them again to BRAM..
Becouse when I just simply conect output to input, it makes a cycle of BRAM to infinite, but I need to change the volume of output, which is coming back to input, to half of its volume..
I read it can be achived by shifting sample to the right, but it makes a lot of noise over the sample..
Im using 16 bit samples
So I'm asking for ideas about how to control volume of sample, everything else I have prepared..
So i find out what was my problem.. I was shifting sample vector right, but I just made it by "0" & sample(15 downto 1) but it was signed, so I had to copy MSB instead of adding just plain "0".. so answer is
sample(15) & sample(15 downto 1)
this make sample half of the original volume.. its like sample * 0,5
I'm trying to interface a Nexys3 board with a VmodTFT via a VHDCI connector. I am pretty new to FPGA design, and although I have experience with micro-controllers. I am trying to approach the whole problem as a FSM. However, I've been stuck on this for quite some time now. What signals constitute my power up sequence? When do I start sampling data? I've looked at the relevant datasheets and they don't make things very clearer. Any help would be greatly appreciated (P.S : I use Verilog for the design).
EDIT:
Sorry for the vagueness of my question. Here's specifically what I am looking at.
For starters, I am going to overlook the touch module. I want to look at the whole setup as a FSM. I am assuming the following states:
1. Setup connection or handshake signals
2. Switch on the LCD
3. Receive pixel data
4. Display video
5. Power off the LCD
Would this be a reasonable FSM? My main concerns are with interpreting the signals. Table 5 in the VmodTFT_rm manual shows a list of signals; however, I am having trouble understanding what signals are for what (This is my first time with display modules). I am going to assume everything prefixed with TFT_ is for the display and everything with TP_ is for the touch panel (Please correct me if I'm wrong). So what signals would I be changing in each state and what would act as inputs?
Now what changes should I make to accommodate the touch panel too?
I understand I am probably asking for too much, but I would greatly appreciate a push in the right direction as I am pretty stuck with this for a long time.
Your question could be filled out a little better, it's not clear exactly what's giving you trouble.
I see two relevant docs online (you may have seen these):
Schematic: https://digilentinc.com/Data/Products/VMOD-TFT/VmodTFT_sch.pdf
User Guide: https://digilentinc.com/Data/Products/VMOD-TFT/VmodTFT_rm.pdf
The user guide explains what signals are part of the Power up sequence
you must wait between 0.5ms and 100ms after driving TFT-EN before you can drive DE and the pixel bus
You must wait 0 to 200ms after setting up valid pixel data to enable the display (with DISP)
You must wait 160ms after enabling DISP before you start pulsing LED-EN (PWM controls the backlight)
Admittedly the documentation doesn't look great and some of the signals names are not consistent, but I think you can figure it out from there.
After looking at the user guide to understand what the signals do, look at the schematic to find the mapping between the signal names and the VHDCI pinout. Then when you connect the VHDCI pinout to your FPGA, look at your FPGA's manual to find mapping between pins on the VHDCI connector and balls of the FPGA, and then you can use the fpga's configuration settings to map an FPGA ball to a logical verilog input to your top module.
Hope that clears things up a bit, but please clarify your question about what you don't understand.
Good day,
I am working on a Stratix III FPGA which contains M9K block memories, the contents of which are conveniently initialised to zero on power-on. This suits my application very well.
Is there a way to reset the contents back to zero without power-cycling/reflashing/etc the FPGA? There seems to be no such option in the megawizard plugin manager, and I would like to avoid wasting a bunch of logic which just goes and sequentially writes zero to every address...
I have looked around and there is no reference to such a mechanism, but I thought I'd ask just in case someone knew a handy trick :] By the way I'm working in VHDL but I should be able to translate any Verilog.
Datasheet (does not contain the answer!) : http://www.altera.com/literature/hb/stx3/stx3_siii51004.pdf
Thanks in advance,
- Thomas
PS: This be my first post here, so if I've violated any etiquette please let me know :)
Sorry, the conventional ways to do that are:
to re-configure the fpga (you could trigger that from within your hardware if you don;t mind the whole thing "disappearing" while it reconfigures)
explicitly write zeros in (as you already suggested)
At the wackier end of the solution space, I guess you could also wire something up to the JTAG port if you already have a microcontroller either in the FPGA or outside - you might be able to overwrite the RAM contents that way too.