Up Down counter code - verilog

Question

I need help in my project which is a counter that counts up or down from 0 to 20. I already did my counter code and it's working in active HDL. But now I need to show the numbers in 7-segment in nexys 3 FPGA board.
I have the code of the segment, but I have a problem when I call the module of segment - it is giving me an error in active HDL. Can you please tell me what is the error?
This is my current code :
module main
#(parameter N=7)
(
input switch,
input button,
input fastclk,
output [3:0] enable,
output reg[6:0] out
);
wire[N:0]count;
wire slowclk;
clock c1(fastclk,slowclk);
Updown u1(switch,button,slowclk,count);
segment s1([3:0]count,[7:4]count,fastclk,enable,out);
endmodule
module clock(fastclk,slowclk); //clock code
input fastclk;
output wire slowclk;
reg[25:0]period_count = 0;
always #(posedge fastclk)
begin
period_count <= period_count + 1;
end
assign slowclk = period_count[25];
endmodule
module Updown // UpDown Counter
#(parameter N=7)
(
input switch,
input button,
input clk,
output reg [N:0]count=8'd0,
);
always #(posedge clk)
begin
if(switch == 1 && button == 1) // Countup from 0 to 20
begin
if(count == 8'd20)
count <= 0 ;
else
count <= count +1;
end
else if(switch == 0 && button == 1) // Countdown from 20 to 0
begin
if(count == 8'd0)
count <= 8'd20 ;
else
count <= count -1;
end
else count <=8'd0;
end
endmodule
module mux(A,B,sel,Y); // 2x1 Multiplexer
input [3:0]A;
input [3:0]B;
input sel;
output [3:0]Y;
reg [3:0]Y;
always #(*)
begin
if(sel==0)
Y=A;
else
Y=B;
end
endmodule
module hex7seg(input wire [3:0]x , output reg[6:0]a_to_g); // Hex to 7seg Code
always #(*)
case(x)
0: a_to_g = 7'b0000001;
1: a_to_g = 7'b1001111;
2: a_to_g = 7'b0010010;
3: a_to_g = 7'b0000110;
4: a_to_g = 7'b1001100;
5: a_to_g = 7'b0100100;
6: a_to_g = 7'b0100000;
7: a_to_g = 7'b0001111;
8: a_to_g = 7'b0000000;
9: a_to_g = 7'b0000100;
'hA: a_to_g = 7'b0001000;
'hB: a_to_g = 7'b1100000;
'hC: a_to_g = 7'b0110001;
'hD: a_to_g = 7'b1000010;
'hE: a_to_g = 7'b0110000;
'hF: a_to_g = 7'b0111000;
default: a_to_g = 7'b0000001;
endcase
endmodule
module segment (a,b,fast,enable,seg7);
input [3:0]a;
input [3:0]b;
input fast;
output [3:0] enable;
output [6:0] seg7;
wire [3:0]e1 = 4'b1110;
wire [3:0]e2 = 4'b1101;
wire slow;
wire [3:0]number;
clock c1(fast,slow);
mux m1(a,b,slow,number);
mux m2(e1,e2,slow,enable);
hex7seg h1(number,seg7);
endmodule

Answer 1

You have a small error in segment module initialization part of code:
segment s1([3:0]count,[7:4]count,fastclk,enable,out);
This part of code should look a little bit different:
segment s1(count[3:0],count[7:4],fastclk,enable,out);

Answer 2

The big issue is:
segment s1([3:0]count,[7:4]count,fastclk,enable,out);
It should be:
segment s1(count[3:0],count[7:4],fastclk,enable,out);
Other option (IEEE Std 1364-2001 auto connect by name (.*)):
segment s1(.a(count[3:0]), .b(count[7:4]), .fast(fastclk), .seg7(out), .*);
Some simulators may complain about initial values on outputs with ANSI style port lists or trailing comma in the port list. So this:
output reg [N:0]count=8'd0,
);
Should be:
output reg [N:0] count
);
initial count=8'd0;
I prefer being able to control the reset in my designs, so I'd prefer:
input reset_n,
output reg [N:0] count
);
always #(posedge clk
// or negedge reset_n // <-- uncomment for asynchronous reset
) begin
if (!reset_n) begin
count=8'd0;
end
else begin
// synchronous code here
end
end
In main you have output reg[6:0] out. Since out is not assigned by an always-block in main (sub-modules don't count), it should be a wire not a reg. This one is a guideline as it is best practice for Verilog, most simulates tolerate it.