1KHz Binary Counter: output stuck at 0000 - verilog

Question

I'm trying to build a 1KHz binary counter in Verilog for use in an FPGA. I want to get it to work in a single .v file before separating each module into it's own file and getting practice in calling modules that way.
As far as I can see, I've set up the logic and the connections properly but after compiling/programming into the FPGA, my hex displays are just stuck at 0 instead of incrementing through.
Can someone please take a look and tell me where I might be going wrong?
Notes:
The input CLK50 and the HEX(0-3) pins have been connected to their proper pins via Pin Assignment.
module IO_Test3(
input CLK50,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3
);
wire CLOCK1;
wire count;
One_KHz_Clock clock(CLK50, CLOCK1);
Counter_16B counter(CLOCK1, count);
Display_Driver_SevenSeg display(CLOCK1,count,HEX0,HEX1,HEX2,HEX3);
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
module Display_Driver_SevenSeg(
input CLOCK_1, // 1KHz clock
input wire count, //16 bit register
output wire [6:0] HEX0,
output wire [6:0] HEX1,
output wire [6:0] HEX2,
output wire [6:0] HEX3
);
reg[15:0] counter;
always#(*)
begin
counter <= count;
end
seg7 Dig0(counter[3:0], HEX0);
seg7 Dig1(counter[7:4], HEX1);
seg7 Dig2(counter[11:8], HEX2);
seg7 Dig3(counter[15:12], HEX3);
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
module seg7(input [3:0] hex, output wire [6:0] segments);
reg[6:0] leds;
always #(*) begin
case (hex)
0: leds = 7'b0111111;
1: leds = 7'b0000110;
2: leds = 7'b1011011;
3: leds = 7'b1001111;
4: leds = 7'b1100110;
5: leds = 7'b1101101;
6: leds = 7'b1111101;
7: leds = 7'b0000111;
8: leds = 7'b1111111;
9: leds = 7'b1100111;
10: leds = 7'b1110111;
11: leds = 7'b1111100;
12: leds = 7'b0111001;
13: leds = 7'b1011110;
14: leds = 7'b1111001;
15: leds = 7'b1110001;
endcase
end
assign segments = ~leds;
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
module Counter_16B(input CLOCK_1, //1KHz clock
output wire[15:0] count);
reg [15:0] r_reg;
wire [15:0] r_next;
initial
begin
r_reg = 0;
end
always #(posedge CLOCK_1)
begin
r_reg <= r_next;
end
assign count = r_reg;
assign r_next = r_reg + 1;
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
module One_KHz_Clock(input CLOCK_50, //50MHz clock signal
output reg CLOCK_1);
reg[27:0] counter = 28'd0;
parameter divisor = 28'd50000;
always#(posedge CLOCK_50)
begin
counter <= counter + 28'd1;
if(counter >= (divisor - 1))
counter <= 28'd0;
CLOCK_1 <= (counter < divisor/2)?1'b1:1'b0;
end
endmodule

Answer 1

The count variable needs to be a vector [15:0] was one bit.
Verified using a small testbench.
The design counts now.
module IO_Test3(
input CLK50,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3
);
wire CLOCK1;
wire [15:0] count;
One_KHz_Clock clock(CLK50, CLOCK1);
Counter_16B counter(CLOCK1, count);
Display_Driver_SevenSeg display(CLOCK1,count,HEX0,HEX1,HEX2,HEX3);
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
module Display_Driver_SevenSeg(
input CLOCK_1, // 1KHz clock
input wire [15:0] count, //16 bit register
output wire [6:0] HEX0,
output wire [6:0] HEX1,
output wire [6:0] HEX2,
output wire [6:0] HEX3
);
reg[15:0] counter;
always#(*)
begin
counter = count;
end
seg7 Dig0(counter[3:0], HEX0);
seg7 Dig1(counter[7:4], HEX1);
seg7 Dig2(counter[11:8], HEX2);
seg7 Dig3(counter[15:12], HEX3);
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
module seg7(input [3:0] hex, output wire [6:0] segments);
reg[6:0] leds;
always #(*) begin
case (hex)
0: leds = 7'b0111111;
1: leds = 7'b0000110;
2: leds = 7'b1011011;
3: leds = 7'b1001111;
4: leds = 7'b1100110;
5: leds = 7'b1101101;
6: leds = 7'b1111101;
7: leds = 7'b0000111;
8: leds = 7'b1111111;
9: leds = 7'b1100111;
10: leds = 7'b1110111;
11: leds = 7'b1111100;
12: leds = 7'b0111001;
13: leds = 7'b1011110;
14: leds = 7'b1111001;
15: leds = 7'b1110001;
endcase
end
assign segments = ~leds;
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
module Counter_16B(input CLOCK_1, //1KHz clock
output wire[15:0] count);
reg [15:0] r_reg;
wire [15:0] r_next;
initial
begin
r_reg = 0;
end
always #(posedge CLOCK_1)
begin
r_reg <= r_next;
end
assign count = r_reg;
assign r_next = r_reg + 1;
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
module One_KHz_Clock(input CLOCK_50, //50MHz clock signal
output reg CLOCK_1);
reg[27:0] counter = 28'd0;
parameter divisor = 28'd5;
always#(posedge CLOCK_50)
begin
counter <= counter + 28'd1;
if(counter >= (divisor - 1))
counter <= 28'd0;
CLOCK_1 <= (counter < divisor/2)?1'b1:1'b0;
end
endmodule
Here is the SV testbench (runs on edaplayground.com):
module tb ();
bit CLK50;
logic [6:0] HEX0;
logic [6:0] HEX1;
logic [6:0] HEX2;
logic [6:0] HEX3 ;
always
#5 CLK50 = ! CLK50;
initial
begin
#10000;
$finish;
end
initial
begin
$dumpfile("dump.vcd");
$dumpvars;
end
IO_Test3
u1(.*);
endmodule