I'm writing a verilog code for the convolution layer in a CNN, and i'm getting the following errors:
1)ERROR:HDLCompiler:257 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 52: Cannot assign to non-variable max_irow
2)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 52: Procedural assignment to a non-register max_irow is not
permitted, left-hand side should be reg/integer/time/genvar
3)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 52: Procedural assignment to a non-register max_irow is not
permitted, left-hand side should be reg/integer/time/genvar
4)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 52: Procedural assignment to a non-register max_irow is not
permitted, left-hand side should be reg/integer/time/genvar
5)ERROR:HDLCompiler:257 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 54: Cannot assign to non-variable max_icol
6)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 54: Procedural assignment to a non-register max_icol is not
permitted, left-hand side should be reg/integer/time/genvar
7)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 54: Procedural assignment to a non-register max_icol is not
permitted, left-hand side should be reg/integer/time/genvar
8)ERROR:HDLCompiler:257 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 56: Cannot assign to non-variable max_krow
9)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 56: Procedural assignment to a non-register max_krow is not
permitted, left-hand side should be reg/integer/time/genvar
10)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 56: Procedural assignment to a non-register max_krow is not
permitted, left-hand side should be reg/integer/time/genvar
11)ERROR:HDLCompiler:257 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 58: Cannot assign to non-variable max_kcol
12)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 58: Procedural assignment to a non-register max_kcol is not
permitted, left-hand side should be reg/integer/time/genvar
13)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 58: Procedural assignment to a non-register max_kcol is not
permitted, left-hand side should be reg/integer/time/genvar
14)ERROR:HDLCompiler:255 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 60: Cannot assign to memory sum directly
15)ERROR:HDLCompiler:747 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 60: Range is not allowed in a prefix
16)ERROR:HDLCompiler:698 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 60: Part-select of memory image is not allowed
17)ERROR:HDLCompiler:971 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 60: Illegal operand for operator *
18)ERROR:HDLCompiler:1373 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 60: Unpacked value/target cannot be used in assignment
19)ERROR:HDLCompiler:598 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 21: Module <convolution_normal> ignored due to previous errors.
My verilog code is:
module convolution_normal(sum,clk,image,kernel,bias);
/*suppose we have input image of size 15*16*3, and a kernel of size 3*3*3*/
parameter reg max_irow = 15; //number of input rows
parameter reg max_icol = 16; //number of input columns
parameter reg max_idepth = 3; //depth of input
parameter reg max_krow = 3; //number of kernel rows
parameter reg max_kcol = 3; //number of kernel columns
parameter reg max_kdepth = 3; //depth of kernel
parameter reg max_orow = 15; //number of output rows
parameter reg max_ocol = 16; //number of output columns
parameter reg max_odepth = 3; //depth of output
input clk;
input bias = 0;
input image[max_irow:0][max_icol:0][max_idepth:0];
input kernel[max_krow:0][max_kcol:0][max_kdepth:0];
output reg sum[max_orow:0][max_ocol:0][max_odepth:0];
always#(posedge clk)
begin
//NOTE: ++ does not exist in verilog
for (max_irow = 0; max_irow <= max_irow; max_irow = max_irow+1)
begin
for (max_icol = 0; max_icol <= max_icol; max_icol = max_icol+1)
begin
for(max_krow = 0; max_krow <= max_krow; max_krow = max_krow+1)
begin
for(max_kcol = 0; max_kcol <= max_kcol; max_kcol = max_kcol+1)
begin
sum = image[max_irow:0][max_icol:0][max_idepth:0]*kernel[max_krow:0][max_kcol:0][max_kdepth:0];
end
end
end
end
end
endmodule
Can someone please solve this issue?
Your loops are incorrect :
for example :
for (max_irow = 0; max_irow <= max_irow; max_irow = max_irow+1)
max irow is a parameter not a variable. It cannot be incremented or assigned.
Same problem with all other loops.
You should modify them in this way :
integer iter;
for (iter = 0; iter <= max_irow; iter = iter+1)
Related
I have some code as follows:
module trapverilog(
input CLK,
input signed [7:0] SIGNAL,
input signed [7:0] x,
input signed [7:0] SUM, // OUT pins are mapped to SUM pins on board
output reg OUTP,
output reg OUT1,
output reg OUT2,
output reg OUT3,
output reg OUT4,
output reg OUT5,
output reg OUT6,
output reg OUT7
);
reg[7:0] yregone;
reg[7:0] yregtwo;
reg[7:0] innerSumOutput;
reg[7:0] innerSignal;
reg[7:0] innerSum;
function [7:0] multiply;
input [7:0] a;
input [7:0] b;
wire [15:0] a1, a2, a3, a4, a5, a6, a7, a8;
assign a1 = (b[0]==1'b1) ? {8'b00000000, a} : 16'b0000000000000000;
assign a2 = (b[1]==1'b1) ? {7'b0000000, a, 1'b0} : 16'b0000000000000000;
assign a3 = (b[2]==1'b1) ? {6'b000000, a, 2'b00} : 16'b0000000000000000;
assign a4 = (b[3]==1'b1) ? {5'b00000, a, 3'b000} : 16'b0000000000000000;
assign a5 = (b[4]==1'b1) ? {4'b0000, a, 4'b0000} : 16'b0000000000000000;
assign a6 = (b[5]==1'b1) ? {3'b000, a, 5'b00000} : 16'b0000000000000000;
assign a7 = (b[6]==1'b1) ? {2'b00, a, 6'b000000} : 16'b0000000000000000;
assign a8 = (b[7]==1'b1) ? {1'b0, a, 7'b0000000} : 16'b0000000000000000;
multiply = a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8;
endfunction
always #(posedge CLK)
begin
yregtwo <= yregone;
yregone <= innerSignal;
if (yregone != 0)
begin
innerSum <= multiply((yregone + yregtwo), x); //treats x as plain h, change if treated as h/2 // multiply defined by function shift-adds
innerSumOutput <= (innerSum <<< 1) + innerSum; // <<< is signed one bit shift which = /2
if (innerSumOutput[0] == 1)
begin
OUTP <= 1;
end
OUT1 <= innerSumOutput[1];
OUT2 <= innerSumOutput[2];
OUT3 <= innerSumOutput[3];
OUT4 <= innerSumOutput[4];
OUT5 <= innerSumOutput[5];
OUT6 <= innerSumOutput[6];
OUT7 <= innerSumOutput[7];
end
end
endmodule
The basic purpose of the code is to perform the trapezoidal integration method. The code compiled until I added the multiply function, which is a shift-add multiply function. I changed this because I was told in chat that * wouldn't work properly on an FPGA. I read a bit and found this method, but it could very well be an X-Y problem there.
I adapted the function from this module I found and then changed it into a function following the examples here. The errors the program is producing look like a selection of syntax errors mixed in with complaints about "procedural continuous assignments":
ERROR:HDLCompiler:806 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 45: Syntax error near "wire".
ERROR:HDLCompiler:1366 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 42: Multiple statement function/task without begin/end not supported in this mode of Verilog
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 46: <a1> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 46: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 47: <a2> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 47: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 48: <a3> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 48: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 49: <a4> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 49: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 50: <a5> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 50: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 51: <a6> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 51: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 52: <a7> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 52: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 53: <a8> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 53: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 54: <a1> is not declared.
I am fairly new to programming Verilog and am rather unsure what the problem is. I am also unsure as to whether or not this will work with signed numbers. Any help would be appreciated. Thanks!
You cannot declare wires inside a function. Use reg instead.
Do not use assign inside a function.
See my blog for more details about the difference between wires and regs.
I want to create a test bench for my ALU circuit. When i compile it, i get some errors:
module ALU_TB();
logic [7:0] A, B, w;
logic [2:0] s, n;
logic co, ci, si;
wire ov, neg, zero, gt, eq;
ALU alu8(A, B, s, si, ci, n, co, ov, zero, neg, gt, eq, w);
assign A = 8'b10000000, B = 8'b0, s = 3'b0, ci = 1'b0, si = 1'b0, n = 3'b011;
initial begin
integer i;
for (i = 0; i < 7; i = i + 1) begin
s = s + 3'b001;
repeat(8) #59 A = {A[0], A[7:1]};
#59 B = 8'b10000000; A = 8'b01011010;
repeat(8) #59 B = {~B[0], B[7:1]};
end
end
endmodule
These are the compile errors for lines 12, 13, 14, 14, 15:
** Error: (vlog-3838) variable 's' written by continuous and procedural assignments.
** Error: (vlog-3838) variable'A' written by continuous and procedural assignments.
** Error: (vlog-3838) Variable 'B' written by continuous and procedural assignments.
** Error: (vlog-3838) Variable 'A' written by continuous and procedural assignments.
** Error: (vlog-3838) Variable 'B' written by continuous and procedural assignments.
What these errors mean?
You are using 'A', 'B' , 'S' in continuous assignment (assign) and also in procedural block(initial). A variable cannot be used in continuous and procedural assignment at the same time.
By the way, logic of your code is not correct. For example when you assign B=0, it means B will be 0 all the time (That's why it is called continuous assignment!). But you are changing B in initial block!
It seems that you wanted to initialize signals using assign which is totally wrong. Initial blocks are used for this purpose.
And finally, put the declaration of variable 'i' outside of initial block.
integer i;
initial begin
A = 8'b10000000;
B = 8'b0;
s = 3'b0;
ci = 1'b0;
si = 1'b0;
n = 3'b011;
#1 for (i = 0; i < 7; i = i + 1) begin
// your code here
end
end
I am trying to implement RSA on and virtex 5 FPGA using verilog. Xilinx ISE logs aren't very descriptive. I'm using a CORDIC 4.0 IP core and a Random number generator. I've been working on this for the past week and I can't seem to get it straight.
MAIN FILE
`include "GARO.v"
module RSA_Encryption(RST_N,CLOCK,CTEXTPUB,RANDP,RANDQ,RANDE,PRIME_CHECK,PRIME_CHECKED,MESSAGE,RECEIVED);
//******************************************************
//Declarations
//******************************************************
reg RST_N;
input wire CLOCK;
input wire [31:0] PRIME_CHECKED;
output wire [31:0] PRIME_CHECK;
input wire [31:0] RANDP;
input wire [31:0] RANDQ;
input wire [31:0] RANDE;
integer randp;
integer randq;
integer phi;
integer e;
integer d;
integer mod = 0;
integer i = 0;
input wire [31:0] MESSAGE;
input wire [31:0] RECEIVED;
integer message;
integer received;
integer sqroot;
output wire [31:0] CTEXTPUB;
RST_N = 1;
d = 1;
//******************************************************
//******************************************************
//Calling random number generator module to get random numbers via wires: RANDP, RANDQ and RANDE
//******************************************************
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDP);
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDQ);
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDE);
//******************************************************
//******************************************************
//Assigning random numbers from respective wires to integer variables randp, randq and e
//******************************************************
e = RANDE;
randp = RANDP;
randq = RANDQ;
//******************************************************
//******************************************************
//Check whether randp is prime or not
//******************************************************
do begin
Square_Root_CORDIC_Core_IP (CLOCK,sqroot,randp);
for(i = 0 ; i <= sqroot ; i++)
begin
if((sqroot%i) == 0)
begin
break;
end
end
break;
randp = RANDP;
end while(1);
//******************************************************
//******************************************************
//Check whether randq is prime or not
//******************************************************
do begin
Square_Root_CORDIC_Core_IP (CLOCK,sqroot,randq);
for(int i = 0;i<=sqroot,i++)
begin
if((sqroot%i) == 0)
begin
break;
end
end
break;
randq = RANDQ;
end while(1);
//*******************************************************
//*******************************************************
//Computing 'phi'
//*******************************************************
phi = (randp-1)(randq-1);
//*******************************************************
//*******************************************************
//Selecting 'e'
//*******************************************************
do begin
e = RANDE;
end while(e < phi && e > 1);
//*******************************************************
//*******************************************************
//Checking if gcd(e,phi) is 1
//*******************************************************
do begin
rem = phi%e;
if(rem == 0 && e == 1)
begin
break;
end
else
begin
do begin
e = RANDE;
end while(e > phi && e > 1);
end
phi = e;
e = rem;
end while(1);
//***********************************************
//***********************************************
//Computing 'n'
//***********************************************
n = randp*randq;
//***********************************************
//***********************************************
//Calculating 'd'
//***********************************************
do begin
mod = (d*e)%phi;
d = d+1;
end while(mod != 1);
//***********************************************
//***********************************************
//Computing Ciphertext using public key i.e (n,e)
//***********************************************
message = MESSAGE;
do begin
message = message*message;
e--;
end while(e != 0);
CTEXTPUB = message%n;
//***********************************************
//***********************************************
//Decrypting ciphertext using private key i.e (n,d)
//***********************************************
received = RECEIVED;
do begin
received = received*received;
d = d-1;
end while (d != 0);
received = received%n;
//************************************************
endmodule
RANDOM NUMBER GENERATOR
module fibonacci_lfsr_nbit
#(parameter BITS = 32)
(
input clk,
input rst_n,
output reg [31:0] data
);
reg [31:0] data_next;
always_comb begin
data_next = data;
repeat(BITS) begin
data_next = {(data_next[31]^data_next[1]), data_next[31:1]};
end
end
always_ff #(posedge clk or negedge rst_n) begin
if(!rst_n)
data <= 32'h1f1f;
else
data <= data_next;
end
end
endmodule
HERE'S THE IP CORE API
`timescale 1 ns/1 ps
module Square_Root_CORDIC_Core_IP (
clk, x_out, x_in
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [31 : 0] x_out;
input [31 : 0] x_in;
LOGS
Started : "Behavioral Check Syntax".
Determining files marked for global include in the design...
Running vlogcomp...
Command Line: vlogcomp -work isim_temp -intstyle ise -prj G:/Xilinx_Projects/first_project/RSA/RSA_Encryption_stx_beh.prj
Determining compilation order of HDL files
Analyzing Verilog file "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" into library isim_temp
ERROR:HDLCompiler:806 - "GARO.v" Line 11: Syntax error near "begin".
ERROR:HDLCompiler:525 - "GARO.v" Line 14: Inconsistent dimension in declaration
ERROR:HDLCompiler:806 - "GARO.v" Line 14: Syntax error near "}".
ERROR:HDLCompiler:598 - "GARO.v" Line 1: Module <fibonacci_lfsr_nbit> ignored due to previous errors.
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 32: Syntax error near "=".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 57: Syntax error near "=".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 70: Syntax error near ")".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 71: Syntax error near "+".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 75: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 78: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 92: Syntax error near ")".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 93: Syntax error near "i".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 149: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 154: Syntax error near "begin".
ERROR:HDLCompiler:53 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 4: <RST_N> is not a port.
ERROR:HDLCompiler:1059 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 230: d is an unknown type
ERROR:HDLCompiler:1059 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 232: received is an unknown type
ERROR:HDLCompiler:598 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 4: Module <RSA_Encryption> ignored due to previous errors.
Verilog file G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v ignored due to errors
Process "Behavioral Check Syntax" failed
Process "Behavioral Check Syntax" failed
There are a lot of things wrong here.
The most important problem, though, is that you are trying to write Verilog code as if it's a procedural programming language. This won't work; Verilog is a hardware description language. You cannot use constructs like for and while loops to implement iteration in hardware; these operations must be implemented as clocked logic.
Get a good textbook on FPGA design and work through it. You have a lot to learn.
If this is coursework: contact your professor or a teaching assistant now. You are not going to make your deadline.
module booth(num1,num2,prod);
input [22:0] num1,num2;
output [45:0] prod;
reg [22:0]num1_bar;
reg [46:0]sub_1;
reg [22:0]temp;
reg [22:0]result;
reg [1:0]sel;
reg [22:0]add;
reg [22:0]zeros;
assign temp = ~ num1;
assign num1_bar = temp + "00000000000000000000001";
assign sub_1 = {zeros[22:0], num2, "0"};
integer i;
always #* begin
for( i = 0; i < 22; i = i+1) begin
assign sel = sub_1[1:0];
if(sel == "10") begin
assign add = sub_1[46:24] + num1_bar;
assign sub_1 ={add[22],add,sub_1[23:1]};
end
elseif(sel == "01") begin
assign add = sub_1[46:24] + num1 ;
assign sub_1 ={add[22],add,sub_1[23:1]};
end
else begin
assign sub_1= {sub_1[46] ,sub_1[46:1]};
end
end
endmodule
I am trying to implement a floating point multiplier using carry look ahead adder and booth multiplier. After running the above code following errors has occurred only for the booth multiplier.
Please help me out.
ERRORS:
Summary Tue Apr 7 15:25:28 2015
Summary New
ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 45. Syntax error near "begin".
ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 49. Syntax error near "else".
ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 54. Syntax error near "endmodule".
INFO ProjectMgmt:1845 - Analyzing Verilog file "D:/XILINX PROGRAM/bth/booth.v" into library work
You seem to have a confusion between VHDL and Verilog.
Vector constants in Verilog are in the form: Y'zXXXXXXX where Y is the number of bits of the vector, z is the base (b for binary, d for decimal, h for hexadecimal), and XXXX is the constante value in the specified base.
else if must separated
For example, the line:
if(sel == "10") begin
Must be rewritten as:
if(sel == 2'b10) begin
For large vectors, you can ommit the size specifier, and write the constant as this:
assign num1_bar = temp + 'b00000000000000000000001;
You are missing an end matching the begin of the always block.
(Once you have fixed that, you will see that there are other errors, too. See mcleod_ideafix's answer.)
module ram_1_verilog(input EnA,input EnB,
input WeA, input WeB,
input Oe,
input clk);
LINE :25 input [7:0] Addr_a; //Error
LINE :26 input [7:0]Addr_b; //Error
LINE :27 input reg [7:0] dout1; //Error
LINE :28 output reg [7:0] dout_2; //Error
reg [7:0] ram [255:0];
always #(posedge clk)
begin
if(EnA == 1 && WeA == 1) begin
LINE 35 ram(Addr_a) <= dout1; //Error
end
end
always #(posedge clk)
begin
if(EnB == 1 && WeB == 0) begin
LINE : 44 dout_2 <= ram(Addr_b); //Error
end
end
endmodule
Errors:
Syntax error near "<=". line 35
Line 25: Port Addr_a is not defined Verilog file C:/Documents and Settings/verilog_examples/ram_1_verilog.v ignored due to errors
Line 25: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 26: Port Addr_b is not defined
Line 26: Port Addr_b is not defined
Line 26: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 27: Port dout1 is not defined
Line 27: Non-net port dout1 cannot be of mode input
Line 27: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 28: Port dout_2 is not defined
Line 28: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 35: dout1 is not a task
Line 44: ram is not a function.
Line 44: ram expects 0 arguments.
Line 44: Cannot assign an unpacked type to a packed type.
I'm working on a dpram, but I'm getting errors in Verilog. Please help me figure out the error.
Lines 35 and 44 - you've made twice the same mistake, explained to you by Tim.
Lines 25-28 are flagged, because Addr_a, Addr_b, dout1 and dout_2 are not declared in port declaration list and then are defined as input/output.
One issue I see is that you are attempting to do array selection with parenthesis, when it should use square brackets:
Change from:
LINE 35 ram(Addr_a) <= dout1; // error
to:
LINE 35 ram[Addr_a] <= dout1;
I don't see any errors on line 25-28, not sure why those are being flagged.