module mult(a, b, p);
input [16:0] a;
input [16:0] b;
output p;
wire [31:0] p;
reg i;
wire pv;
wire bp;
assign pv = 32'b0;
assign bp = {16'b0,b} ;
initial begin
for (i = 0; i < 32 ; i = i + 1)
begin
if (a[i] == 1'b1)
begin
pv <= pv + bp;
end
bp <= bp << 1 ;
end
end
assign p = pv;
endmodule
I get the following error while compiling the code,
line 37 Reference to scalar wire 'pv' is not a legal reg or variable lvalue
line 37 Illegal left hand side of nonblocking assignment
line 39 Reference to scalar wire 'bp' is not a legal reg or variable lvalue
line 39 Illegal left hand side of nonblocking assignment
Pls help.
Left hand side of assignment in always and initial blocks must be registers. pv and bp are wires instead of registers.
you cannot put a variable in left hand side of assign and always block at the same time. Because always needs registers and assign needs wires.
I see obvious semantic mistakes in your code . You need to study basics of Verilog. You put assign which means you expect a continuous assignment but an initial block is executed just once in the beginning of simulation.
By the way output is wire by default. you can declare it as output [31:0] p;
I am trying to implement RSA on and virtex 5 FPGA using verilog. Xilinx ISE logs aren't very descriptive. I'm using a CORDIC 4.0 IP core and a Random number generator. I've been working on this for the past week and I can't seem to get it straight.
MAIN FILE
`include "GARO.v"
module RSA_Encryption(RST_N,CLOCK,CTEXTPUB,RANDP,RANDQ,RANDE,PRIME_CHECK,PRIME_CHECKED,MESSAGE,RECEIVED);
//******************************************************
//Declarations
//******************************************************
reg RST_N;
input wire CLOCK;
input wire [31:0] PRIME_CHECKED;
output wire [31:0] PRIME_CHECK;
input wire [31:0] RANDP;
input wire [31:0] RANDQ;
input wire [31:0] RANDE;
integer randp;
integer randq;
integer phi;
integer e;
integer d;
integer mod = 0;
integer i = 0;
input wire [31:0] MESSAGE;
input wire [31:0] RECEIVED;
integer message;
integer received;
integer sqroot;
output wire [31:0] CTEXTPUB;
RST_N = 1;
d = 1;
//******************************************************
//******************************************************
//Calling random number generator module to get random numbers via wires: RANDP, RANDQ and RANDE
//******************************************************
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDP);
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDQ);
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDE);
//******************************************************
//******************************************************
//Assigning random numbers from respective wires to integer variables randp, randq and e
//******************************************************
e = RANDE;
randp = RANDP;
randq = RANDQ;
//******************************************************
//******************************************************
//Check whether randp is prime or not
//******************************************************
do begin
Square_Root_CORDIC_Core_IP (CLOCK,sqroot,randp);
for(i = 0 ; i <= sqroot ; i++)
begin
if((sqroot%i) == 0)
begin
break;
end
end
break;
randp = RANDP;
end while(1);
//******************************************************
//******************************************************
//Check whether randq is prime or not
//******************************************************
do begin
Square_Root_CORDIC_Core_IP (CLOCK,sqroot,randq);
for(int i = 0;i<=sqroot,i++)
begin
if((sqroot%i) == 0)
begin
break;
end
end
break;
randq = RANDQ;
end while(1);
//*******************************************************
//*******************************************************
//Computing 'phi'
//*******************************************************
phi = (randp-1)(randq-1);
//*******************************************************
//*******************************************************
//Selecting 'e'
//*******************************************************
do begin
e = RANDE;
end while(e < phi && e > 1);
//*******************************************************
//*******************************************************
//Checking if gcd(e,phi) is 1
//*******************************************************
do begin
rem = phi%e;
if(rem == 0 && e == 1)
begin
break;
end
else
begin
do begin
e = RANDE;
end while(e > phi && e > 1);
end
phi = e;
e = rem;
end while(1);
//***********************************************
//***********************************************
//Computing 'n'
//***********************************************
n = randp*randq;
//***********************************************
//***********************************************
//Calculating 'd'
//***********************************************
do begin
mod = (d*e)%phi;
d = d+1;
end while(mod != 1);
//***********************************************
//***********************************************
//Computing Ciphertext using public key i.e (n,e)
//***********************************************
message = MESSAGE;
do begin
message = message*message;
e--;
end while(e != 0);
CTEXTPUB = message%n;
//***********************************************
//***********************************************
//Decrypting ciphertext using private key i.e (n,d)
//***********************************************
received = RECEIVED;
do begin
received = received*received;
d = d-1;
end while (d != 0);
received = received%n;
//************************************************
endmodule
RANDOM NUMBER GENERATOR
module fibonacci_lfsr_nbit
#(parameter BITS = 32)
(
input clk,
input rst_n,
output reg [31:0] data
);
reg [31:0] data_next;
always_comb begin
data_next = data;
repeat(BITS) begin
data_next = {(data_next[31]^data_next[1]), data_next[31:1]};
end
end
always_ff #(posedge clk or negedge rst_n) begin
if(!rst_n)
data <= 32'h1f1f;
else
data <= data_next;
end
end
endmodule
HERE'S THE IP CORE API
`timescale 1 ns/1 ps
module Square_Root_CORDIC_Core_IP (
clk, x_out, x_in
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [31 : 0] x_out;
input [31 : 0] x_in;
LOGS
Started : "Behavioral Check Syntax".
Determining files marked for global include in the design...
Running vlogcomp...
Command Line: vlogcomp -work isim_temp -intstyle ise -prj G:/Xilinx_Projects/first_project/RSA/RSA_Encryption_stx_beh.prj
Determining compilation order of HDL files
Analyzing Verilog file "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" into library isim_temp
ERROR:HDLCompiler:806 - "GARO.v" Line 11: Syntax error near "begin".
ERROR:HDLCompiler:525 - "GARO.v" Line 14: Inconsistent dimension in declaration
ERROR:HDLCompiler:806 - "GARO.v" Line 14: Syntax error near "}".
ERROR:HDLCompiler:598 - "GARO.v" Line 1: Module <fibonacci_lfsr_nbit> ignored due to previous errors.
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 32: Syntax error near "=".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 57: Syntax error near "=".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 70: Syntax error near ")".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 71: Syntax error near "+".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 75: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 78: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 92: Syntax error near ")".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 93: Syntax error near "i".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 149: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 154: Syntax error near "begin".
ERROR:HDLCompiler:53 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 4: <RST_N> is not a port.
ERROR:HDLCompiler:1059 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 230: d is an unknown type
ERROR:HDLCompiler:1059 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 232: received is an unknown type
ERROR:HDLCompiler:598 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 4: Module <RSA_Encryption> ignored due to previous errors.
Verilog file G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v ignored due to errors
Process "Behavioral Check Syntax" failed
Process "Behavioral Check Syntax" failed
There are a lot of things wrong here.
The most important problem, though, is that you are trying to write Verilog code as if it's a procedural programming language. This won't work; Verilog is a hardware description language. You cannot use constructs like for and while loops to implement iteration in hardware; these operations must be implemented as clocked logic.
Get a good textbook on FPGA design and work through it. You have a lot to learn.
If this is coursework: contact your professor or a teaching assistant now. You are not going to make your deadline.
module booth(num1,num2,prod);
input [22:0] num1,num2;
output [45:0] prod;
reg [22:0]num1_bar;
reg [46:0]sub_1;
reg [22:0]temp;
reg [22:0]result;
reg [1:0]sel;
reg [22:0]add;
reg [22:0]zeros;
assign temp = ~ num1;
assign num1_bar = temp + "00000000000000000000001";
assign sub_1 = {zeros[22:0], num2, "0"};
integer i;
always #* begin
for( i = 0; i < 22; i = i+1) begin
assign sel = sub_1[1:0];
if(sel == "10") begin
assign add = sub_1[46:24] + num1_bar;
assign sub_1 ={add[22],add,sub_1[23:1]};
end
elseif(sel == "01") begin
assign add = sub_1[46:24] + num1 ;
assign sub_1 ={add[22],add,sub_1[23:1]};
end
else begin
assign sub_1= {sub_1[46] ,sub_1[46:1]};
end
end
endmodule
I am trying to implement a floating point multiplier using carry look ahead adder and booth multiplier. After running the above code following errors has occurred only for the booth multiplier.
Please help me out.
ERRORS:
Summary Tue Apr 7 15:25:28 2015
Summary New
ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 45. Syntax error near "begin".
ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 49. Syntax error near "else".
ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 54. Syntax error near "endmodule".
INFO ProjectMgmt:1845 - Analyzing Verilog file "D:/XILINX PROGRAM/bth/booth.v" into library work
You seem to have a confusion between VHDL and Verilog.
Vector constants in Verilog are in the form: Y'zXXXXXXX where Y is the number of bits of the vector, z is the base (b for binary, d for decimal, h for hexadecimal), and XXXX is the constante value in the specified base.
else if must separated
For example, the line:
if(sel == "10") begin
Must be rewritten as:
if(sel == 2'b10) begin
For large vectors, you can ommit the size specifier, and write the constant as this:
assign num1_bar = temp + 'b00000000000000000000001;
You are missing an end matching the begin of the always block.
(Once you have fixed that, you will see that there are other errors, too. See mcleod_ideafix's answer.)
module ram_1_verilog(input EnA,input EnB,
input WeA, input WeB,
input Oe,
input clk);
LINE :25 input [7:0] Addr_a; //Error
LINE :26 input [7:0]Addr_b; //Error
LINE :27 input reg [7:0] dout1; //Error
LINE :28 output reg [7:0] dout_2; //Error
reg [7:0] ram [255:0];
always #(posedge clk)
begin
if(EnA == 1 && WeA == 1) begin
LINE 35 ram(Addr_a) <= dout1; //Error
end
end
always #(posedge clk)
begin
if(EnB == 1 && WeB == 0) begin
LINE : 44 dout_2 <= ram(Addr_b); //Error
end
end
endmodule
Errors:
Syntax error near "<=". line 35
Line 25: Port Addr_a is not defined Verilog file C:/Documents and Settings/verilog_examples/ram_1_verilog.v ignored due to errors
Line 25: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 26: Port Addr_b is not defined
Line 26: Port Addr_b is not defined
Line 26: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 27: Port dout1 is not defined
Line 27: Non-net port dout1 cannot be of mode input
Line 27: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 28: Port dout_2 is not defined
Line 28: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 35: dout1 is not a task
Line 44: ram is not a function.
Line 44: ram expects 0 arguments.
Line 44: Cannot assign an unpacked type to a packed type.
I'm working on a dpram, but I'm getting errors in Verilog. Please help me figure out the error.
Lines 35 and 44 - you've made twice the same mistake, explained to you by Tim.
Lines 25-28 are flagged, because Addr_a, Addr_b, dout1 and dout_2 are not declared in port declaration list and then are defined as input/output.
One issue I see is that you are attempting to do array selection with parenthesis, when it should use square brackets:
Change from:
LINE 35 ram(Addr_a) <= dout1; // error
to:
LINE 35 ram[Addr_a] <= dout1;
I don't see any errors on line 25-28, not sure why those are being flagged.
I'm trying to create a modules that simulates 4-bit multiplier without using multiplication (*) , need just to use Half and Full adders , so I succeeded to program the solution from some instance , this is the code :
module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout = a^b;
assign cout = (a&b);
endmodule
module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout =(a^b^cin);
assign cout = ((a&b)|(a&cin)|(b&cin));
endmodule
module multiply4bits(product,inp1,inp2,clock,reset,load);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
input clock;
input reset;
input load;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
always # (posedge clock )
begin
if(reset == 1)
begin
// something to reset
end
else if (load == 1)
begin
product[0] = (inp1[0]&inp2[0]);
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,(inp1[1]&inp2[1]),(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
end
end
endmodule
The problem is that I get a lot of errors from the lines inside the condition if(load == 1)
when I test the code.
here are the errors :
Line 34: Procedural assignment to a non-register product is not permitted, left-hand side should be reg/integer/time/genvar
Line 35: Instantiation is not allowed in sequential area except checker instantiation
Line 36: Instantiation is not allowed in sequential area except checker instantiation
Line 37: Instantiation is not allowed in sequential area except checker instantiation
.
.
Line 46: Instantiation is not allowed in sequential area except checker instantiation
If I remove the always # .. and write the code outside of it the code works perfectly !
but i must use the clock in order to get this code work just on load = 1 .
If anyone can help me I'll be very thankful .
You can also do this way:
module mul4(ans,aa,bb,clk,load,);
input [3:0]aa,bb;
input load,clk;
output [7:0]ans;
reg rst;
always #(posedge clk)
begin
if(load)
rst=0;
else
rst=1;
end
multiply4bits mm(ans,aa,bb,cl,rst);
endmodule
module multiply4bits(product,inp1,inp2,clock,reset);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
input clock;
input reset;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
assign product[0]= (inp1[0]&inp2[0]);
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,(inp1[1]&inp2[1]),(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
endmodule
module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout = a^b;
assign cout = (a&b);
endmodule
module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout =(a^b^cin);
assign cout = ((a&b)|(a&cin)|(b&cin));
endmodule
Hope it'll help.