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I'm writing a verilog code for the convolution layer in a CNN, and i'm getting the following errors:
1)ERROR:HDLCompiler:257 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 52: Cannot assign to non-variable max_irow
2)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 52: Procedural assignment to a non-register max_irow is not
permitted, left-hand side should be reg/integer/time/genvar
3)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 52: Procedural assignment to a non-register max_irow is not
permitted, left-hand side should be reg/integer/time/genvar
4)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 52: Procedural assignment to a non-register max_irow is not
permitted, left-hand side should be reg/integer/time/genvar
5)ERROR:HDLCompiler:257 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 54: Cannot assign to non-variable max_icol
6)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 54: Procedural assignment to a non-register max_icol is not
permitted, left-hand side should be reg/integer/time/genvar
7)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 54: Procedural assignment to a non-register max_icol is not
permitted, left-hand side should be reg/integer/time/genvar
8)ERROR:HDLCompiler:257 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 56: Cannot assign to non-variable max_krow
9)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 56: Procedural assignment to a non-register max_krow is not
permitted, left-hand side should be reg/integer/time/genvar
10)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 56: Procedural assignment to a non-register max_krow is not
permitted, left-hand side should be reg/integer/time/genvar
11)ERROR:HDLCompiler:257 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 58: Cannot assign to non-variable max_kcol
12)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 58: Procedural assignment to a non-register max_kcol is not
permitted, left-hand side should be reg/integer/time/genvar
13)ERROR:HDLCompiler:1660 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 58: Procedural assignment to a non-register max_kcol is not
permitted, left-hand side should be reg/integer/time/genvar
14)ERROR:HDLCompiler:255 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 60: Cannot assign to memory sum directly
15)ERROR:HDLCompiler:747 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 60: Range is not allowed in a prefix
16)ERROR:HDLCompiler:698 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 60: Part-select of memory image is not allowed
17)ERROR:HDLCompiler:971 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 60: Illegal operand for operator *
18)ERROR:HDLCompiler:1373 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 60: Unpacked value/target cannot be used in assignment
19)ERROR:HDLCompiler:598 - "D:\DSD_CEP_verilog\convolution_normal.v"
Line 21: Module <convolution_normal> ignored due to previous errors.
My verilog code is:
module convolution_normal(sum,clk,image,kernel,bias);
/*suppose we have input image of size 15*16*3, and a kernel of size 3*3*3*/
parameter reg max_irow = 15; //number of input rows
parameter reg max_icol = 16; //number of input columns
parameter reg max_idepth = 3; //depth of input
parameter reg max_krow = 3; //number of kernel rows
parameter reg max_kcol = 3; //number of kernel columns
parameter reg max_kdepth = 3; //depth of kernel
parameter reg max_orow = 15; //number of output rows
parameter reg max_ocol = 16; //number of output columns
parameter reg max_odepth = 3; //depth of output
input clk;
input bias = 0;
input image[max_irow:0][max_icol:0][max_idepth:0];
input kernel[max_krow:0][max_kcol:0][max_kdepth:0];
output reg sum[max_orow:0][max_ocol:0][max_odepth:0];
always#(posedge clk)
begin
//NOTE: ++ does not exist in verilog
for (max_irow = 0; max_irow <= max_irow; max_irow = max_irow+1)
begin
for (max_icol = 0; max_icol <= max_icol; max_icol = max_icol+1)
begin
for(max_krow = 0; max_krow <= max_krow; max_krow = max_krow+1)
begin
for(max_kcol = 0; max_kcol <= max_kcol; max_kcol = max_kcol+1)
begin
sum = image[max_irow:0][max_icol:0][max_idepth:0]*kernel[max_krow:0][max_kcol:0][max_kdepth:0];
end
end
end
end
end
endmodule
Can someone please solve this issue?
Your loops are incorrect :
for example :
for (max_irow = 0; max_irow <= max_irow; max_irow = max_irow+1)
max irow is a parameter not a variable. It cannot be incremented or assigned.
Same problem with all other loops.
You should modify them in this way :
integer iter;
for (iter = 0; iter <= max_irow; iter = iter+1)
I have some code as follows:
module trapverilog(
input CLK,
input signed [7:0] SIGNAL,
input signed [7:0] x,
input signed [7:0] SUM, // OUT pins are mapped to SUM pins on board
output reg OUTP,
output reg OUT1,
output reg OUT2,
output reg OUT3,
output reg OUT4,
output reg OUT5,
output reg OUT6,
output reg OUT7
);
reg[7:0] yregone;
reg[7:0] yregtwo;
reg[7:0] innerSumOutput;
reg[7:0] innerSignal;
reg[7:0] innerSum;
function [7:0] multiply;
input [7:0] a;
input [7:0] b;
wire [15:0] a1, a2, a3, a4, a5, a6, a7, a8;
assign a1 = (b[0]==1'b1) ? {8'b00000000, a} : 16'b0000000000000000;
assign a2 = (b[1]==1'b1) ? {7'b0000000, a, 1'b0} : 16'b0000000000000000;
assign a3 = (b[2]==1'b1) ? {6'b000000, a, 2'b00} : 16'b0000000000000000;
assign a4 = (b[3]==1'b1) ? {5'b00000, a, 3'b000} : 16'b0000000000000000;
assign a5 = (b[4]==1'b1) ? {4'b0000, a, 4'b0000} : 16'b0000000000000000;
assign a6 = (b[5]==1'b1) ? {3'b000, a, 5'b00000} : 16'b0000000000000000;
assign a7 = (b[6]==1'b1) ? {2'b00, a, 6'b000000} : 16'b0000000000000000;
assign a8 = (b[7]==1'b1) ? {1'b0, a, 7'b0000000} : 16'b0000000000000000;
multiply = a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8;
endfunction
always #(posedge CLK)
begin
yregtwo <= yregone;
yregone <= innerSignal;
if (yregone != 0)
begin
innerSum <= multiply((yregone + yregtwo), x); //treats x as plain h, change if treated as h/2 // multiply defined by function shift-adds
innerSumOutput <= (innerSum <<< 1) + innerSum; // <<< is signed one bit shift which = /2
if (innerSumOutput[0] == 1)
begin
OUTP <= 1;
end
OUT1 <= innerSumOutput[1];
OUT2 <= innerSumOutput[2];
OUT3 <= innerSumOutput[3];
OUT4 <= innerSumOutput[4];
OUT5 <= innerSumOutput[5];
OUT6 <= innerSumOutput[6];
OUT7 <= innerSumOutput[7];
end
end
endmodule
The basic purpose of the code is to perform the trapezoidal integration method. The code compiled until I added the multiply function, which is a shift-add multiply function. I changed this because I was told in chat that * wouldn't work properly on an FPGA. I read a bit and found this method, but it could very well be an X-Y problem there.
I adapted the function from this module I found and then changed it into a function following the examples here. The errors the program is producing look like a selection of syntax errors mixed in with complaints about "procedural continuous assignments":
ERROR:HDLCompiler:806 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 45: Syntax error near "wire".
ERROR:HDLCompiler:1366 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 42: Multiple statement function/task without begin/end not supported in this mode of Verilog
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 46: <a1> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 46: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 47: <a2> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 47: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 48: <a3> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 48: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 49: <a4> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 49: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 50: <a5> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 50: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 51: <a6> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 51: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 52: <a7> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 52: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 53: <a8> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 53: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 54: <a1> is not declared.
I am fairly new to programming Verilog and am rather unsure what the problem is. I am also unsure as to whether or not this will work with signed numbers. Any help would be appreciated. Thanks!
You cannot declare wires inside a function. Use reg instead.
Do not use assign inside a function.
See my blog for more details about the difference between wires and regs.
I am trying to implement RSA on and virtex 5 FPGA using verilog. Xilinx ISE logs aren't very descriptive. I'm using a CORDIC 4.0 IP core and a Random number generator. I've been working on this for the past week and I can't seem to get it straight.
MAIN FILE
`include "GARO.v"
module RSA_Encryption(RST_N,CLOCK,CTEXTPUB,RANDP,RANDQ,RANDE,PRIME_CHECK,PRIME_CHECKED,MESSAGE,RECEIVED);
//******************************************************
//Declarations
//******************************************************
reg RST_N;
input wire CLOCK;
input wire [31:0] PRIME_CHECKED;
output wire [31:0] PRIME_CHECK;
input wire [31:0] RANDP;
input wire [31:0] RANDQ;
input wire [31:0] RANDE;
integer randp;
integer randq;
integer phi;
integer e;
integer d;
integer mod = 0;
integer i = 0;
input wire [31:0] MESSAGE;
input wire [31:0] RECEIVED;
integer message;
integer received;
integer sqroot;
output wire [31:0] CTEXTPUB;
RST_N = 1;
d = 1;
//******************************************************
//******************************************************
//Calling random number generator module to get random numbers via wires: RANDP, RANDQ and RANDE
//******************************************************
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDP);
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDQ);
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDE);
//******************************************************
//******************************************************
//Assigning random numbers from respective wires to integer variables randp, randq and e
//******************************************************
e = RANDE;
randp = RANDP;
randq = RANDQ;
//******************************************************
//******************************************************
//Check whether randp is prime or not
//******************************************************
do begin
Square_Root_CORDIC_Core_IP (CLOCK,sqroot,randp);
for(i = 0 ; i <= sqroot ; i++)
begin
if((sqroot%i) == 0)
begin
break;
end
end
break;
randp = RANDP;
end while(1);
//******************************************************
//******************************************************
//Check whether randq is prime or not
//******************************************************
do begin
Square_Root_CORDIC_Core_IP (CLOCK,sqroot,randq);
for(int i = 0;i<=sqroot,i++)
begin
if((sqroot%i) == 0)
begin
break;
end
end
break;
randq = RANDQ;
end while(1);
//*******************************************************
//*******************************************************
//Computing 'phi'
//*******************************************************
phi = (randp-1)(randq-1);
//*******************************************************
//*******************************************************
//Selecting 'e'
//*******************************************************
do begin
e = RANDE;
end while(e < phi && e > 1);
//*******************************************************
//*******************************************************
//Checking if gcd(e,phi) is 1
//*******************************************************
do begin
rem = phi%e;
if(rem == 0 && e == 1)
begin
break;
end
else
begin
do begin
e = RANDE;
end while(e > phi && e > 1);
end
phi = e;
e = rem;
end while(1);
//***********************************************
//***********************************************
//Computing 'n'
//***********************************************
n = randp*randq;
//***********************************************
//***********************************************
//Calculating 'd'
//***********************************************
do begin
mod = (d*e)%phi;
d = d+1;
end while(mod != 1);
//***********************************************
//***********************************************
//Computing Ciphertext using public key i.e (n,e)
//***********************************************
message = MESSAGE;
do begin
message = message*message;
e--;
end while(e != 0);
CTEXTPUB = message%n;
//***********************************************
//***********************************************
//Decrypting ciphertext using private key i.e (n,d)
//***********************************************
received = RECEIVED;
do begin
received = received*received;
d = d-1;
end while (d != 0);
received = received%n;
//************************************************
endmodule
RANDOM NUMBER GENERATOR
module fibonacci_lfsr_nbit
#(parameter BITS = 32)
(
input clk,
input rst_n,
output reg [31:0] data
);
reg [31:0] data_next;
always_comb begin
data_next = data;
repeat(BITS) begin
data_next = {(data_next[31]^data_next[1]), data_next[31:1]};
end
end
always_ff #(posedge clk or negedge rst_n) begin
if(!rst_n)
data <= 32'h1f1f;
else
data <= data_next;
end
end
endmodule
HERE'S THE IP CORE API
`timescale 1 ns/1 ps
module Square_Root_CORDIC_Core_IP (
clk, x_out, x_in
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [31 : 0] x_out;
input [31 : 0] x_in;
LOGS
Started : "Behavioral Check Syntax".
Determining files marked for global include in the design...
Running vlogcomp...
Command Line: vlogcomp -work isim_temp -intstyle ise -prj G:/Xilinx_Projects/first_project/RSA/RSA_Encryption_stx_beh.prj
Determining compilation order of HDL files
Analyzing Verilog file "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" into library isim_temp
ERROR:HDLCompiler:806 - "GARO.v" Line 11: Syntax error near "begin".
ERROR:HDLCompiler:525 - "GARO.v" Line 14: Inconsistent dimension in declaration
ERROR:HDLCompiler:806 - "GARO.v" Line 14: Syntax error near "}".
ERROR:HDLCompiler:598 - "GARO.v" Line 1: Module <fibonacci_lfsr_nbit> ignored due to previous errors.
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 32: Syntax error near "=".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 57: Syntax error near "=".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 70: Syntax error near ")".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 71: Syntax error near "+".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 75: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 78: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 92: Syntax error near ")".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 93: Syntax error near "i".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 149: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 154: Syntax error near "begin".
ERROR:HDLCompiler:53 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 4: <RST_N> is not a port.
ERROR:HDLCompiler:1059 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 230: d is an unknown type
ERROR:HDLCompiler:1059 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 232: received is an unknown type
ERROR:HDLCompiler:598 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 4: Module <RSA_Encryption> ignored due to previous errors.
Verilog file G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v ignored due to errors
Process "Behavioral Check Syntax" failed
Process "Behavioral Check Syntax" failed
There are a lot of things wrong here.
The most important problem, though, is that you are trying to write Verilog code as if it's a procedural programming language. This won't work; Verilog is a hardware description language. You cannot use constructs like for and while loops to implement iteration in hardware; these operations must be implemented as clocked logic.
Get a good textbook on FPGA design and work through it. You have a lot to learn.
If this is coursework: contact your professor or a teaching assistant now. You are not going to make your deadline.
I am coding that put the value of 'd' into 'z' whenever 'clk' is changed to '1'.
For example,
clk=0 d= 15, z= x
clk=1 d= 20, z= 20
clk=0 d= 25, z= 20
clk=1 d= 30, z= 30
it put value of 'd' into 'z' whenever clk is '1'.
So below is code that does repeat it for 20 times for random numbers.
module lab9;
reg [31:0] d;
reg clk, enable, flag;
wire [31:0] z;
reg [31:0] e;
register #(32) mine(z, d, clk, enable);
always begin
#5 clk = ~clk;
end
initial
#1 $monitor("%5d: clk=%b,d=%d,z=%d,expect=%d", $time,clk,d,z, e);
initial begin
clk=0;
flag = $value$plusargs("enable=%b", enable);
repeat (20) begin
#2 d = $random;
end
$finish;
end
endmodule
And the output I get:
1: clk=0,d= x,z= x,expect= x
2: clk=0,d= 303379748,z= x,expect= x
4: clk=0,d=3230228097,z= x,expect= x
5: clk=1,d=3230228097,z=3230228097,expect= x
6: clk=1,d=2223298057,z=3230228097,expect= x
8: clk=1,d=2985317987,z=3230228097,expect= x
10: clk=0,d= 112818957,z=3230228097,expect= x
12: clk=0,d=1189058957,z=3230228097,expect= x
14: clk=0,d=2999092325,z=3230228097,expect= x
15: clk=1,d=2999092325,z=2999092325,expect= x
16: clk=1,d=2302104082,z=2999092325,expect= x
18: clk=1,d= 15983361,z=2999092325,expect= x
20: clk=0,d= 114806029,z=2999092325,expect= x
22: clk=0,d= 992211318,z=2999092325,expect= x
24: clk=0,d= 512609597,z=2999092325,expect= x
25: clk=1,d= 512609597,z= 512609597,expect= x
26: clk=1,d=1993627629,z= 512609597,expect= x
28: clk=1,d=1177417612,z= 512609597,expect= x
30: clk=0,d=2097015289,z= 512609597,expect= x
32: clk=0,d=3812041926,z= 512609597,expect= x
34: clk=0,d=3807872197,z= 512609597,expect= x
35: clk=1,d=3807872197,z=3807872197,expect= x
36: clk=1,d=3574846122,z=3807872197,expect= x
38: clk=1,d=1924134885,z=3807872197,expect= x
40: clk=0,d=3151131255,z=3807872197,expect= x
On Line 6 of this output need to be '2223298057' but still have value of previous 'z' even though its clk is set to '1'.
How can I fix this?
It would seem from the behaviour of the outputs you have presented that
register #(32) mine(z, d, clk, enable);
is a set of 32 D-type flip-flops, which given its name and the names of the signals you have connected also seems to be the case. It would have been easier to answer your question if you had provided the code for register.
So, if register is indeed a set of 32 D-type flip-flops, you would not expect z to change at time 6. That is not how any kind of flip-flop behaves: the output of a flip-flop only changes on one (rising or falling) edge of a clock.
Given these D-type flip-flops were present before you started this exercise, it would seem that you are changing d far too quickly. You ought to be changing it once per clock (clk) cycle, ie once every #10. In other words, try chaninging
#2 d = $random;
to
#10 d = $random;
Your register is already working correctly. Registers are edge-triggered; there is no clock edge between time steps 5 and 6, so the value of z is not updated.
If you want z to be updated continuously as long as the clock is high, you want a latch, not a register. Be forewarned, however, that timing analysis is much more difficult in designs which include latches, and as such they should usually be avoided.
I'm trying to create a modules that simulates 4-bit multiplier without using multiplication (*) , need just to use Half and Full adders , so I succeeded to program the solution from some instance , this is the code :
module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout = a^b;
assign cout = (a&b);
endmodule
module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout =(a^b^cin);
assign cout = ((a&b)|(a&cin)|(b&cin));
endmodule
module multiply4bits(product,inp1,inp2,clock,reset,load);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
input clock;
input reset;
input load;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
always # (posedge clock )
begin
if(reset == 1)
begin
// something to reset
end
else if (load == 1)
begin
product[0] = (inp1[0]&inp2[0]);
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,(inp1[1]&inp2[1]),(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
end
end
endmodule
The problem is that I get a lot of errors from the lines inside the condition if(load == 1)
when I test the code.
here are the errors :
Line 34: Procedural assignment to a non-register product is not permitted, left-hand side should be reg/integer/time/genvar
Line 35: Instantiation is not allowed in sequential area except checker instantiation
Line 36: Instantiation is not allowed in sequential area except checker instantiation
Line 37: Instantiation is not allowed in sequential area except checker instantiation
.
.
Line 46: Instantiation is not allowed in sequential area except checker instantiation
If I remove the always # .. and write the code outside of it the code works perfectly !
but i must use the clock in order to get this code work just on load = 1 .
If anyone can help me I'll be very thankful .
You can also do this way:
module mul4(ans,aa,bb,clk,load,);
input [3:0]aa,bb;
input load,clk;
output [7:0]ans;
reg rst;
always #(posedge clk)
begin
if(load)
rst=0;
else
rst=1;
end
multiply4bits mm(ans,aa,bb,cl,rst);
endmodule
module multiply4bits(product,inp1,inp2,clock,reset);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
input clock;
input reset;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
assign product[0]= (inp1[0]&inp2[0]);
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,(inp1[1]&inp2[1]),(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
endmodule
module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout = a^b;
assign cout = (a&b);
endmodule
module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout =(a^b^cin);
assign cout = ((a&b)|(a&cin)|(b&cin));
endmodule
Hope it'll help.